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1、CC253x System-on-Chip Solution for 2.4 GHzIEEE 802.15.4 and ZigBeeApplicationsUsers GuideLiterature Number:SWRU191April 20092SWRU191April 2009Submit Documentation FeedbackContentsPreface.131Introduction.151.1Overview.161.1.1CPU and Memory.171.1.2Clocks and Power Management.171.1.3Peripherals.171.1.4
2、Radio.181.2Applications.1928051 CPU.212.18051 CPU Introduction.222.2Memory.222.2.1Memory Map.222.2.2CPU Memory Space.242.2.3Physical Memory.252.2.4XDATA Memory Access.302.2.5Memory Arbiter.302.3CPU Registers.302.3.1Data Pointers.312.3.2Registers R0R7.312.3.3Program Status Word.312.3.4Accumulator.322
3、.3.5B Register.322.3.6Stack Pointer.322.4Instruction Set Summary.322.5Interrupts.362.5.1Interrupt Masking.362.5.2Interrupt Processing.402.5.3Interrupt Priority.423Debug Interface.453.1Debug Mode.463.2Debug Communication.463.3Debug Commands.483.4Lock Bits.483.4.1Debug Configuration.493.4.2Debug Statu
4、s.493.4.3Hardware Breakpoints.513.4.4Flash Programming.513.5Debug Interface and Power Modes.523.6Registers.524Power Management and Clocks.53SWRU191April 2009Contents3Submit Documentation F4.1Power Management Introduction.544.1.1Active and Idle Mode.544.1.2PM1.554.1.3PM2.554.1.4PM3.554.2Power-Managem
5、ent Control.554.3Power-Management Registers.564.4Oscillators and Clocks.594.4.1Oscillators.594.4.2System Clock.594.4.332 kHz Oscillators.604.4.4Oscillator and Clock Registers.604.5Timer Tick Generation.624.6Data Retention.625Reset.635.1Power-On Reset and Brownout Detector.645.2Clock-Loss Detector.64
6、6Flash Controller.656.1Flash Memory Organization.666.2Flash Write.666.2.1Flash-Write Procedure.666.2.2Writing Multiple Times to a Word.676.2.3DMA Flash Write.676.2.4CPU Flash Write.686.3Flash Page Erase.686.3.1Performing Flash Erase From Flash Memory.696.4Flash DMA Trigger.696.5Flash Controller Regi
7、sters.697I/O Ports.717.1Unused I/O Pins.727.2Low I/O Supply Voltage.727.3General-Purpose I/O.727.4General-Purpose I/O Interrupts.727.5General-Purpose I/O DMA.737.6Peripheral I/O.737.6.1Timer 1.747.6.2Timer 3.747.6.3Timer 4.747.6.4USART 0.757.6.5USART 1.757.6.6ADC.767.7Debug Interface.767.832 kHz XOS
8、C Input.767.9Radio Test Output Signals.767.10Power-Down Signal MUX(PMUX).767.11I/O Registers.768DMA Controller.854ContentsSWRU191April 2009Submit Documentation F8.1DMA Operation.868.2DMA Configuration Parameters.888.2.1Source Address.888.2.2Destination Address.888.2.3Transfer Count.888.2.4VLEN Setti
9、ng.898.2.5Trigger Event.898.2.6Source and Destination Increment.898.2.7DMA Transfer Mode.908.2.8DMA Priority.908.2.9Byte or Word Transfers.908.2.10Interrupt Mask.908.2.11Mode 8 Setting.908.3DMA Configuration Setup.908.4Stopping DMA Transfers.918.5DMA Interupts.918.6DMA Configuration Data Structure.9
10、18.7DMA Memory Access.918.8DMA Registers.949Timer 1(16-Bit Timer).979.116-Bit Counter.989.2Timer 1 Operation.989.3Free-Running Mode.989.4Modulo Mode.999.5Up/Down Mode.999.6Channel Mode Control.999.7Input Capture Mode.1009.8Output Compare Mode.1009.9IR Signal Generation and Learning.1059.9.1Introduct
11、ion.1059.9.2Modulated Codes.1059.9.3Non-Modulated Codes.1069.9.4Learning.1079.9.5Other Considerations.1079.10Timer 1 Interrupts.1079.11Timer 1 DMA Triggers.1079.12Timer 1 Registers.1089.13Accessing Timer 1 Registers as Array.11210Timer 3 and Timer 4(8-Bit Timers).11310.18-Bit Timer Counter.11410.2Ti
12、mer 3/Timer 4 Mode Control.11410.2.1Free-Running Mode.11410.2.2Down Mode.11410.2.3Modulo Mode.11410.2.4Up/Down Mode.11410.3Channel Mode Control.11410.4Input Capture Mode.11510.5Output Compare Mode.115SWRU191April 2009Contents5Submit Documentation F10.6Timer 3 and Timer 4 Interrupts.11510.7Timer 3 an
13、d Timer 4 DMA Triggers.11610.8Timer 3 and Timer 4 Registers.11611Sleep Timer.12111.1General.12211.2Timer Compare.12211.3Timer Capture.12211.4Sleep Timer Registers.12312ADC.12512.1ADC Introduction.12612.2ADC Operation.12612.2.1ADC Inputs.12612.2.2ADC Conversion Sequences.12712.2.3Single ADC Conversio
14、n.12712.2.4ADC Operating Modes.12712.2.5ADC Conversion Results.12812.2.6ADC Reference Voltage.12812.2.7ADC Conversion Timing.12812.2.8ADC Interrupts.12812.2.9ADC DMA Triggers.12812.2.10ADC Registers.12913Random-Number Generator.13313.1Introduction.13413.2Random-Number-Generator Operation.13413.2.1Ps
15、eudorandom Sequence Generation.13413.2.2Seeding.13413.2.3CRC16.13513.3Random-Number-Generator Registers.13514AES Coprocessor.13714.1AES Operation.13814.2Key and IV.13814.3Padding of Input Data.13814.4Interface to CPU.13814.5Modes of Operation.13814.6CBC-MAC.13914.7CCM Mode.13914.8Sharing the AES Cop
16、rocessor Between Layers.14114.9AES Interrupts.14114.10AES DMA Triggers.14114.11AES Registers.14115Watchdog Timer.14315.1Watchdog Mode.14415.2Timer Mode.14415.3Watchdog Timer Register.14416USART.14716.1UART Mode.14816.1.1UART Transmit.1486ContentsSWRU191April 2009Submit Documentation F16.1.2UART Rece
17、ive.14816.1.3UART Hardware Flow Control.14916.1.4UART Character Format.14916.2SPI Mode.14916.2.1SPI Master Operation.14916.2.2SPI Slave Operation.15016.3SSN Slave-Select Pin.15016.4Baud-Rate Generation.15016.5USART Flushing.15116.6USART Interrupts.15116.7USART DMA Triggers.15116.8USART Registers.152
18、17USB Controller.15717.1USB Introduction.15817.2USB Enable.15817.348 MHz USB PLL.15817.4USB Interrupts.15917.5Endpoint 0.15917.6Endpoint-0 Interrupts.15917.6.1Error Conditions.16017.6.2SETUP Transactions(IDLE State).16017.6.3IN Transactions(TX state).16017.6.4OUT Transactions(RX State).16117.7Endpoi
19、nts 15.16117.7.1FIFO Management.16117.7.2Double Buffering.16217.7.3FIFO Access.16317.7.4Endpoint 15 Interupts.16317.7.5Bulk/Interrupt IN Endpoint.16417.7.6Isochronous IN Endpoint.16417.7.7Bulk/Interrupt OUT Endpoint.16417.7.8Isochronous OUT Endpoint.16417.8DMA.16517.9USB Reset.16517.10Suspend and Re
20、sume.16517.11Remote Wake-Up.16517.12USB Registers.16618Timer 2(MAC Timer).17318.1Timer Operation.17418.1.1General.17418.1.2Up Counter.17418.1.3Timer Overflow.17418.1.4Timer Delta Increment.17418.1.5Timer Compare.17418.1.6Overflow Count.17418.1.7Overflow Count Update.17518.1.8Overflow Count Overflow.
21、17518.1.9Overflow Count Compare.175SWRU191April 2009Contents7Submit Documentation F18.1.10Capture Input.17518.2Interrupts.17518.3Event Outputs(DMA Trigger and CSP Events).17618.4Timer Start/Stop Synchronization.17618.4.1General.17618.4.2Timer Synchronous Stop.17618.4.3Timer Synchronous Start.17618.5
22、Timer 2 Registers.17719Radio.18119.1RF Core.18219.1.1Interrupts.18219.1.2Interrupt Registers.18219.2FIFO Access.18619.3DMA.18619.4Memory Map.18619.4.1RX FIFO.18719.4.2TX FIFO.18719.4.3Frame-Filtering and Source-Matching Memory Map.18719.5Frequency and Channel Programming.18819.6IEEE 802.15.4-2006 Mo
23、dulaltion Format.18819.7IEEE 802.15.4-2006 Frame Format.19019.7.1PHY Layer.19019.7.2MAC Layer.19019.8Transmit Mode.19119.8.1TX Control.19119.8.2TX State Timing.19119.8.3TX FIFO Access.19119.8.4Retransmission.19219.8.5Error Conditions.19219.8.6TX Flow Diagram.19319.8.7Frame Processing.19419.8.8Synchr
24、onization Header.19419.8.9Frame Length Field.19419.8.10Frame Check Sequence.19419.8.11Interrupts.19519.8.12Clear-Channel Assessment.19519.8.13Output Power Programming.19519.8.14Tips and Tricks.19519.9Receive Mode.19519.9.1RX Control.19519.9.2RX State Timing.19619.9.3Frame Processing.19619.9.4Synchro
25、nization Header and Frame Length Fields.19619.9.5Frame Filtering.19719.9.6Source Address Matching.20019.9.7Frame Check Sequence.20319.9.8Acknowledgement Transmission.20319.10RX FIFO Access.2058ContentsSWRU191April 2009Submit Documentation F19.10.1Using the FIFO and FIFOP.20519.10.2Error Conditions.2
26、0619.10.3RSSI.20619.10.4Link Quality Indication.20719.11Radio Control State Machine.20719.12Random-Number Generation.20919.13Packet Sniffing and Radio Test Output Signals.21019.14Command Strobe/CSMA-CA Processor.21119.14.1Instruction Memory.21119.14.2Data Registers.21219.14.3Program Execution.21219.
27、14.4Interrupt Requests.21219.14.5Random Number Instruction.21219.14.6Running CSP Programs.21219.14.7Registers.21319.14.8Instruction Set Summary.21419.14.9Instruction Set Definition.21519.15Registers.22819.15.1Register Settings Update.22819.15.2Register Access Modes.22919.15.3Register Descriptions.22
28、920Voltage Regulator.24721Available Software.24921.1SmartRF Software for Evaluation( Network Protocol( Network Protocol( Software( Software( Information.257B.1Texas Instruments Low-Power RF Web Site.258B.2Low-Power RF Online Community.258B.3Texas Instruments Low-Power RF Developer Network.258B.4Low-
29、Power RF eNewsletter.258CReferences.259SWRU191April 2009Contents9Submit Documentation FList of Figures1-1CC253x Block Diagram.162-1XDATA Memory Space(Showing SFR and DATA Mapping).232-2CODE Memory Space.242-3CODE Memory Space for Running Code From SRAM.242-4Interrupt Overview.383-1External Debug Int
30、erface Timing.463-2Transmission of One Byte.463-3Typical Command SequenceNo Extra Wait for Response.473-4Typical Command Sequence.Wait for Response.483-5Burst Write Command(First 2 Bytes).514-1Clock System Overview.586-1Flash Write Using DMA.688-1DMA Operation.878-2Variable Length(VLEN)Transfer Opti
31、ons.899-1Free-Running Mode.989-2Modulo Mode.999-3Up/Down Mode.999-4Output Compare Modes,Timer Free-Running Mode.1029-5Output Compare Modes,Timer Modulo Mode.1039-6Output Compare Modes,Timer Up/Down Mode.1049-7Block Diagram of Timers in IR-Generation Mode.1069-8Modulated Waveform Example.1069-9IR Lea
32、rning Board Diagram.10711-1Sleep Timer Capture(Example Using Rising Edge on P0_0).12312-1ADC Block Diagram.12613-1Basic Structure of the Random Number Generator.13414-1Message Authentication Phase Block 0.13914-2Authentication Flag Byte.13914-3Message Encryption Phase Block.14014-4Encryption Flag By
33、te.14017-1USB Controller Block Diagram.15817-2IN/OUT FIFOs.16219-1Modulation.18919-2I/Q Phases When Transmitting a Zero-Symbol Chip Sequence,tC=0.5 s.18919-3Schematic View of the IEEE 802.15.4 Frame Format 1.19019-4Format of the Frame Control Field(FCF).19019-5Frame Data Written to the TX FIFO.19219
34、-6TX Flow.19319-7Transmitted Synchronization Header.19419-8FCS Hardware Implementation.19519-9SFD Signal Timing.19719-10 Filtering Scenarios(Exceptions Generated During Reception).19919-11 Matching Algorithm for Short and Extended Addresses.20119-12 Interrupts Generated by Source Address Matching.20
35、219-13 Data in RX FIFO for Different Settings.20319-14 Acknowledge Frame Format.20319-15 Acknowledgement Timing.20419-16 Command Strobe Timing.20419-17 Behavior of FIFO and FIFOP Signals.20619-18 Main FSM.20819-19 FFT of the Random Bytes.21019-20 Histogram of 20 Million Bytes Generated With the RAND
36、OM Instruction.21010List of FiguresSWRU191April 2009Submit Documentation F19-21 Running a CSP Program.21319-22 Example Hardware Structure for the R*Register Access Mode.229SWRU191April 2009List of Figures11Submit Documentation FList of Tables1Register Bit Conventions.142-1SFR Overview.262-2Overview
37、of XREG Registers.292-3Instruction Set Summary.332-4Instructions That Affect Flag Settings.362-5Interrupts Overview.372-6Priority Level Setting.432-7Interrupt Priority Groups.432-8Interrupt Polling Sequence.443-1Flash Lock-Protection Bit Structure Definition.493-2Debug Commands.493-3Debug Configurat
38、ion.503-4Debug Status.504-1Power Modes.546-1Example Write Sequence.677-1Peripheral I/O Pin Mapping.738-1DMA Trigger Sources.918-2DMA Configuration Data Structure.929-1Initial Compare Output Values(Compare Mode).1019-2Frequency Error Calculation for 38 kHz Carrier.10510-1Initial Compare Output Values
39、(Compare Mode).11516-1Commonly Used Baud-Rate Settings for 32 MHz System Clock.15117-1USB Interrupt Flags Interrupt-Enable Mask Registers.15917-2FIFO Sizes for EP 15.16218-1Internal Registers.17819-1Frame Filtering and Source Matching Memory Map.18719-2IEEE 802.15.4-2006 Symbol-to-Chip Mapping.18919
40、-3FSM State Mapping.20919-4Instruction Set Summary.21419-5Register Overview.22819-6Registers That Require Update From Their Default Value.22919-7Register-Bit Access Modes.22912List of TablesSWRU191April 2009Submit Documentation FeedbackPrefaceSWRU191April 2009Read This FirstAbout This ManualThe CC25
41、3x System-on-Chip solution for 2.4 GHz is suitable for a wide range of applications.These caneasily be built on top of the IEEE 802.15.4 based standard protocols(RemoTI network protocol,TIMACsoftware,and Z-Stack software for ZigBeecompliant solutions)or on top of the proprietary SimpliciTInetwork pr
42、otocol.The usage is,however,not limited to these protocols alone.The CC253x family is,e.g.also suitable for 6LoWPAN and Wireless HART implementations.Each chapter of this manual describes details of a module or peripheral;however,not all features arepresent on all devices of the CC253x family.For de
43、tailed technical numbers,such as power consumption and RF performance,see the device-specificdata sheet.Related Documentation and Software From Texas InstrumentsRelated documentation(e.g.,the CC2530 Data Sheet http:/ be foundin Appendix C.For more information regarding software that can be used with
44、 the CC253x System-on-Chip solution(e.g.,SmartRF software for radio performance and functionality evaluation),see Chapter 21,which alsocontains more information regarding the RemoTI network protocol,the SimpliciTI network protocol,theTIMAC software,and the Z-Stack software.FCC WarningThis equipment
45、is intended for use in a laboratory test environment only.It generates,uses,and canradiate radio frequency energy and has not been tested for compliance with the limits of computingdevices pursuant to subpart J of part 15 of FCC rules,which are designed to provide reasonableprotection against radio
46、frequency interference.Operation of this equipment in other environments maycause interference with radio communications,in which case the user at his own expense will be requiredto take whatever measures may be required to correct this interference.If You Need AssistanceAll technical support is cha
47、nneled through the TI Product Information Centers(PIC)- send an E-mail request,please enter your contact information,along with your request at the followinglink PIC request form.Please also visit the Low Power RF and ZigBee section of the TI E2E Community( you can easily get in touch with other CC2
48、53x users and find FAQs,Design Notes,ApplicationNotes,Videos,etc.You can also see the TI Knowledgebase for Analog&Mixed-Signal.GlossaryAbbreviations used in this user guide can be found in Appendix A.RemoTI,Z-Stack,SimpliciTI,SmartRF are trademarks of Texas Instruments.Microsoft,Windows are trademar
49、ks of Microsoft Corporation.ZigBee is a registered trademark of ZigBee Alliance.SWRU191April 2009Read This First13Submit Documentation FeedbackDDevicesThe CC253x System-on-Chip solution family consists of several devices.The following table provides anoverview and information about the different per
50、ipherals,memory sizes,etc.,of each device.CC253x Family OverviewFeatureCC2530F32/F64/F128/F256CC2531F256FLASH_SIZE32 KB/64 KB/128 KB/256 KB256 KBSRAM_SIZE8 KB8 KBUSBNot includedIncludedLegend:FLASH_SIZE The size of the flash in bytesSRAM_SIZE The size of the SRAM in bytesRegister ConventionsEach SFR