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1、精品文档，仅供学习与交流，如有侵权请联系网站删除外文资料Phase-locked loop Technology ：A phase-locked loop or phase lock loop (PLL) is a control system that generates a signal that has a fixed relation to the phase of a reference signal. A phase-locked loop circuit responds to both the frequency and the phase of the input signa
2、ls, automatically raising or lowering the frequency of a controlled oscillator until it is matched to the reference in both frequency and phase. A phase-locked loop is an example of a control system using negative feedback. In the order of the PLL is the way of made the frequency stability in the se
3、nd up wireless,include VCO and PLL integrated circuits,VCO send up a signal,some of the signal is output,and the other through the frequency division with PLL integrated circuits generate the local signal making compared.In the order to remain the same,its must be remain the phase displacement same.
4、If the phase displacement have some changes,the output of the PLL integrated circuits have some changes too,to controlle VCO until phase difference to restore,make both cotrolled oscillators frequency and phase with input signal which is close-loop electronic circuit keep firm relationship.Phase-loc
5、ked loops are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrate
6、d circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a cycle per second up to many gigahertz. Earliest research towards what became known as the phase-locked loop goes back to 1932, wh
7、en British researchers developed an alternative to Edwin Armstrongs superheterodyne receiver, the Homodyne. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original audio
8、 modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the sa
9、me phase and frequency as the desired signal. The technique was described in 1932, in a paper by H.de Bellescise, in the French journal Onde Electrique. In analog television receivers since at least the late 1930s, phase-locked-loop horizontal and vertical sweep circuits are locked to synchronizatio
10、n pulses in the broadcast signal. When Signetics introduced a line of monolithic integrated circuits that were complete phase-locked loop systems on a chip in 1969, applications for the technique multiplied. A few years later RCA introduced the CD4046 CMOS Micropower Phase-Locked Loop, which became
11、a popular integrated circuit. Applications：Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modu
12、lated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency. Clock recovery ：Some data streams, especially high-speed serial data streams (such as the raw stream of data from the m
13、agnetic head of a disk drive), are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the
14、data stream must have a transition frequently enough to correct any drift in the PLLs oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common. Deskewing ：If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be receiv
15、ed and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating t
16、his delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a Delay-Locked Loop (DLL) is frequently used.Clock generation：Many electronic systems include process
17、ors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be qui
18、te large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz. Spread spectrum： All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on t
19、he emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the ener
20、gy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen by FM
21、 receivers which have a bandwidth of tens of kilohertz.中文翻译锁相环技术：锁相环或锁相回路（ PLL ）是一个信号控制系统，即用来锁定一系列的“参考”信号。锁相环电路响应的频率和相位的输入信号，自动提高或降低频率的控制振荡器，直到符合以上两个频率和阶段。锁相环是一个负反馈控制系统的典型例子。锁相环是为无线电发射中使频率较为稳定的一种方法,主要有VCO (压控振荡器)和锁相环集成电路，压控振荡器给出一个信号，一部分作为输出，另一部分通过分频与锁相环集成电路所产生的本振信号作相位比较。为了保持频率不变,就要求相位差不发生改变，如果有相位差的变
22、化，则锁相环集成电路的电压输出端的电压发生变化，去控制压控振荡器，直到相位差恢复,达到锁频的目的，能使受控振荡器的频率和相位均与输入信号保持确定关系的闭环电子电路。锁相环技术广泛的应用于广播，通信，计算机及其他电子设备中。其作用是对接收到的信号进行处理，并从中提取某个时钟的相位信息，或者说对于接收到的信号。仿制一个时钟信号，使得这两个信号从某个角度来看是同步的（后者说是相干的）。这两个信号可能会产生稳定的频率，从有噪音的频道中恢复信号，或分频时钟脉冲在数字逻辑设计，如微处理器。由于一个集成电路可提供一个完整的锁相环模块，而这一技术又被广泛应用于现代电子设备中，伴随着输出频率来源于一小部分频率，
23、这些频率一个周期每秒最多千兆赫兹。锁相环的研究最早可追溯到1932年，首次由DeBellescize提出的锁相同步检波技术。但首次并未引起普遍的重视。直到1947年，锁相环路才第一次用于电视接收机水平和垂直扫描的同步，并得到了发展。英国研究人员开发了一种替代Edwin Armstrongs的超外差接收器。在零差或超外差接收器系统中，本地振荡器进行了调整，理想的输入频率，再乘以输入信号。由此产生的输出信号包括其原来的音频调制信息。目的是要制订一个替代接收电路，需要比超外差接收机更少的调谐电路。由于本地振荡器将频率迅速改变，自动用振荡器校正信号，保持在同一相位和频率的理想信号。这项技术被称为由 H
24、.de Bellescise 在1932年，在法国电气杂志上刊登。在模拟电视接收器最早起源于自20世纪30年代后期，当时被用于锁相环横向和纵向扫描电路的锁定，与广播信号发生同步脉冲。当Signetics公司于1969年推出了由一系列的单个芯片集成完整的集成电路锁相环系统芯片，这一技术应用的领域成倍增加。几年后的RCA也推出了“ CD4046 ”的CMOS微锁相环，成为一个十分受欢迎的集成电路。应用：锁相环广泛用于同步；在空间通信中，常用于相干载波跟踪和阈值延伸，位同步和符号同步，锁相环也可用于解调调频信号。同样，在无线电发射机中，一个锁相环也可用来合成新的频率从而多一个参考频率，具有同样的稳定
25、作为参考频率。时钟恢复：有些数据流，尤其是高速串行数据流（如原材料的数据流从磁头的硬盘驱动器），被送往没有伴随时钟。接收器会产生一个时钟频率近似参考，然后逐步的过渡直到同数据流的频率相同，这一过程被称为时钟恢复。由于时钟恢复中，数据流常常会有一个频率过渡得不够顺利，而PLL频率的振荡器就用来纠正任何漂移的频率。通常情况下，会使用某种形式的编码使用；8B10B是比较常用的一种编码。时钟传送：如果时钟传送并行数据，时钟可用于采样的数据。因为时钟必须收到并扩增才能推动触发器的样本数据，将进程，温度和电压依赖性延迟时钟之间的边缘检测和数据接收窗口。这种延迟的频率范围的数据可以被发送。消除这种拖延的一种
26、方法是有，包括锁相环的接收端，以便在每一个时钟的数据触发器是相匹配的接收时钟。在这种类型的应用程序，一种特殊形式的锁相环频率称为延迟锁定回路（ DLL ）中经常使用。时钟生成：许多电子系统包括处理器的各种操作在数百兆赫。通常情况下，时钟提供给来自这些处理器的锁相环时钟发生器，乘以低频率的参考时钟（通常是50或100 MHz ）的工作频率的处理器。扩频：所有电子系统发出一些不必要的无线电频率能量。各监管机构（如美国联邦通讯委员会）实施、限制排放的能源和任何干扰造成的。发出的噪音通常出现在谱峰（通常在工作频率的设备和少数谐波中）。系统设计者可以使用扩频锁相环以减少干扰高Q接收机的传播较大能量的频谱。例如，通过改变运行频率向上和向下的一小部分（约1 %），设备运行数百兆赫可以均匀的扩大其干扰几个兆赫的频谱，大大减少了噪音被调频接收器具有几万千赫兹带宽的干扰。【精品文档】第 6 页