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1、精品文档，仅供学习与交流，如有侵权请联系网站删除锁相技术译文翻译英文原名：High Speed Digital Hybrid PLL Frequency Synthesizer译文：高速数字混合锁相环频率合成器年纪专业：08级通信工程 班姓名： 学号： 2011年 5月2日【精品文档】第 15 页英文中文High Speed Digital Hybrid PLL Frequency SynthesizerAbstract：The conventional PLL(Phase locked loop) frequency synthesizer takes a long switching ti

2、me because of the inherent closed-loop structure.The digital hybrid PLL (DH-PLL) which includes the open loop structure into the conventional PLL synthesizer has been studied to overcome this problem.It operates in high speed, but the hardware complexity and power consumption are other serious probl

3、ems since the DLT (digital look-up table) is usually implemented by the ROM which contains the transfer characteristic of VCO (voltage controlled oscillator).This paper proposes a new DH-PLL using a very simple DLT-replacement digital logic instead of the complex ROM-type DLT.Also, a timing synchron

4、ization circuit makes the negligible overshoot and much shorter settling time for the ultra fast switching speed.Also, the hardware complexity and power consumption get decreased to about 28%, compared with the conventional DH-PLL.Key Words: PLL, DLT, Frequency synthesisI. INTRODUCTIONHigh speed fre

5、quency synthesis is very important and is widely used in the electronic and communication system applications.In 1999, El-Ela proposed that additional signal which is a synchronized saw-tooth waveform from the D/A converter is injected into the VCO input of the conventional PLL frequency synthesizer

6、 for the high speed operation 1.However, it needs the optimal slope and duration at every frequency synthesis.To get the high-speed, it is necessary to prepare the precise synchronization of the complicated design.In 2001, H. G. Ryu proposed a simplified structure of the DDFS (direct digital frequen

7、cy synthesizer)-driven PLL for the high switching speed 2.However, there is a problem that the speed of the whole system is limited by PLL.Y. Fouzar proposed a PLL frequency synthesizer of dual loop configuration using frequency-to-voltage converter (FVC) 3.It has a fast switching speed by the PD (p

8、hase detector), FVC using output signal of VCO and the proposed coarse tuning controller.However, H/W complexity is increased for the high switching speed.Also, it shows the fast switching characteristic only when the FVC works well.Another method is pre-tuning one which is called DH-PLL in this stu

9、dy 4.It has very high speed switching property, but H/W complexity and power consumption are increased due to digital look-up table (DLT) which is usually implemented by the ROM including the transfer characteristic of VCO(voltage controlled oscillator).For this reason, this paper proposes a timing

10、synchronization circuit for the rapid frequency synthesis and a very simple DLT replacement digital logic block instead of the complex ROM type DLT for high speed switching and low power consumption.Also, the requisite condition is solved in the proposed method. The fast switching operation at every

11、 the frequency synthesis process is verified by the computer circuit simulation.II. DH-PLL synthesizerAs shown in Fig.1, the open-loop synthesizer is a direct frequency synthesis type that VCO generates the desired output by the FCW (frequency control word) input from the D/A converter.The digital f

12、requency word which is produced from the ROM type DLT (digital look-up table) containing the VCO transfer characteristic goes into D/A converter that generates the DC value corresponding to the desired VCO frequency. Fig. 1. Open-loop frequency synthesizer.The DC value is already found by the voltag

13、e-frequency characteristics of VCO.This open-loop frequency synthesizer has fast switching speed.However, it has the big problems of stability and sensitivity due to the inherent properties of the open loop structure.Therefore, this synthesizer type is not so attractive that this synthesizer is not

14、widely used.Fig. 2. Closed-loop PLL frequency synthesizer.In Fig. 2, FCW (frequency control word) is the division ratio command for frequency synthesis.This structure is very popular and excellent in the aspects of the stability, variety and flexibility.Also, the spurious noise is smaller than other

15、 frequency synthesizer. It takes the longer acquisition time to jump into a new frequency so that the switching speed is low.The switching time gets longer as the generation frequency spacing is increased.DH-PLL frequency synthesizer is shown in Fig.3.Fig.3.DH-PLL using DLT (digital look-up table).T

16、he open-loop structure of the DLT and DAC is combined into the conventional PLL closed-loop structure.In the conventional PLL, the output voltage of LF is fed to the VCO.On the contrary, sum of DAC output voltage and the LF output voltage drives the VCO whenever FCW is changed.Therefore, unlike conv

17、entional PLL, DAC outputs the steady state driving voltage at every new FCW change times so that high speed frequency switching may be possible.However, the DH-PLL has a serious problem of the phase change at every new frequency synthesis.As shown in Fig. 4, the overshoot and the settling time have

18、a trade-off relationship because the output of programmable divider moves into other point after the new FCW start, even though system parameters are previously optimized.So, it has a long settling time and the switching speed gets down.Phase detector inputs are，waveforms of Fig.4 which are used for

19、 the control voltage of LF(loop filter).Therefore, the relationship between and is fixed until a new FCW is made.Fig. 4. Operating signal of DH-PLL.However, if a new FCW is triggered, waveform goes down the low-state (0) in unexpected place, which means a voltage change start of LF.Though there is a

20、 steady state voltage from the DAC, the overshoot happens for a new frequency synthesis so that settling process takes a long time.Like the conventional PLL, the overshoot and settling time get greatly changed for the wider frequency synthesis spacing.In order to overcome this problem, a new timing

21、synchronization circuit is additionally designed and the whole DH-PLL structure is shown in Fig.5.Fig.5. Block diagram of the new proposed DH-PLL.IV. Simulation results and discussionIn this paper, parameters of table 1 and procedure of table 2 are used to verify the switching function of the propos

22、ed DH-PLL circuit structure.FCW is the division ratio. Fig. 9 and 10 are the results of the computer circuit simulations.Division ratio is 8 bit binary value and FCW changes in every 1 msec.Change of the division ratio should be made in the linear region of VCO transfer curve.In Fig.10, the upper wa

23、veform is input driving voltage of VCO, and the lower is output voltage of DAC. As shown in Fig.10, there are very small overshoot and very short settling time in the frequency synthesis transition process because the input to the phase detector is synchronized with the reference input signal irresp

24、ective of how many the programmable divider counts the VCO output.Output voltage of DAC is 0 V at the initial state.Consequently, voltage from DAC and loop filter output are added to drive the VCO so that the desired frequency may be obtained.It can be easily shown that the input driving voltage of

25、VCO is different from the conventional PLL closed-loop structure at the switching times.It is swiftly changed by output voltage of DAC and moved into the steady state driving voltage in a very shorter time whenever FCW varies.From these results, it is shown that DHPLL has very high speed switching f

26、unction.Also, we can compare the proposed DLT-replacement block with the conventional ROM type DLT in the aspects of the circuit complexity.V. ConclusionIn this paper, a DH-PLL synthesizer using simple digital logic circuit instead of ROM type DLT block is proposed to overcome the circuit complexity

27、 and power consumption of the conventional DH-PLL.In fact, DLT block is a burden of hardware complexity and takes a long access time to speed down the switching operation.In addition, there is a necessary condition that the first frequency control word should be same at the initial operation. So, th

28、e proposed structure solves the requisite condition and is verified by computer simulation.The hardware complexity and power consumption gets decreased to about 28%, as compared with the conventional DH-PLL.Frequency synthesizer of the proposed DH-PLL structure can be used for the fast frequency hop

29、ping system, electronic and communication systems.REFERENCES1 El-Ela, M.A. High speed PLL frequency synthesizer with synchronous frequency sweep, NRSC99. Proceedings of the Sixteenth National, pp.23-25, Feb. 1999.2 H. G. Ryu, Y. Y. Kim, H. M. Yu and S. B. Ryu, “Design of DDFS-driven PLL Frequency Sy

30、nthesizer with Reduced Complexity,” IEEE Transactions on Consumer Electronics, Vol. 47, No.1, Feb. 2001.3 Fouzar, Y. , Sawan, M. , Savaria, Y. A new fully integrated CMOS phase-locked loop with low jitter and fast lock time, ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Circuits and Sy

31、stems, Vol.2, pp.253-256, May 2000.4 David M. Materna, “A Lightweight Fast Hopping Synthesizer For EHF Satellite Applications,” Military Communications Conference, MILCOM 95, Conference Record, IEEE, Vol. 2, pp 752-759, 1995.高速数字混合锁相环频率合成器摘要：传统的锁相环频率合成器需要很长的切换时间,因为其内在的闭环结构。目前已经研发的一种数字混合锁相环来解决这一问题在传统

32、的锁相环频率合成器中加入开环结构。它可以高速运行，但硬件复杂度和功耗是一个严重的问题，因为它的数字查找表（包含压控振荡器的传输特性）在ROM中频繁执行。 本文提出一种新的数字混合锁相环使用一种简单的数字查找表代替复杂的ROM型数字查找表。此外，定时同步电路使得环路超调量很小且建立时间短，从而保证了超高速切换速度。同时,硬件复杂度和功耗比传统的数字混合锁相环（DH-PLL）大约降低28%。关键词：锁相环（PLL），数值查找表（DLT），频率合成1简介高速频率合成是一种非常重要的技术,被广泛地应用在电子和通信系统应用。在1999年,El-Ela提出在传统锁相环频率合成器压控振荡器的输入端注入额外的

33、信号从D/A转换器上得到的同步锯齿波可以使它高速度运行【1】。但是，该锯齿波在每一次频率合成时需要最理想的斜率和持续时间。要得到高运行速度,事先做好复杂设计的精确同步是必要的。2001年,H.G.Ryu提出了一种简化结构的直接数字频率合成器(DDFS)驱动的高转换速度锁相环 【2】。但是,有一个问题,整个系统的速度是受锁相环限制的。Y.Fouzar提出了一种使用频率电压转换器(FVC)具有双重回路结构的锁相环频率合成器【3】。因为鉴相器(PD)， FVC利用了压控振荡器的输出信号和我们提出的粗调控制器，所以它具有快速切换速度。但是,因为有高速系统转换速度使得H / W的复杂性增加了。另外，结果

34、表明只有FVC工作状态良好时系统才有较高切换速度。另一种方法是做预先调整也就是本项研究中的DH-PLL 【4】。它具有高速切换的特性，但是因为数字查找表(DLT)的原因，H / W复杂度和功耗明显增大了，因为DLT经常被ROM执行，DLT中包含压控振荡器(VCO)的传输特性。介于以上原因, 为得到较高切换速度和低功耗，本文提出了一种新的快速定时同步频率合成电路，用一个非常简单的DLT替代数字逻辑块，而不用复杂的ROM型(DLT)。同时,在该方法中所需必要条件也解决了，频率合成过程的高切换速度在计算机电路仿真中已经得到验证了。2.DH-PLL合成器图1中所示的开环频率合成技术是一种直接频率合成方

35、式，在频率控制字（FCW）控制下VCO产生了期望的输出,VCO输入来自于D / A转换器。该数字频率控制字是由ROM类型的包含压控振荡器传输特性的数字查找表（DLT)产生的，进入D / A转换器,生成与预期的压控振荡器的频率值相对应的直流电压。图1 .开环频率合成器。直流电压值已经根据VCO的电压频率特性建立了。该开环频率合成器具有高切换速度。但是, 由于开环结构的固有特性,该频率合成器在稳定性和灵敏度方面还有比较大的问题。因此,这种合成器类型缺乏吸引力,该合成器没有广泛应用。图 2.闭合回路PLL 频率合成器。在图2中，频率控制字（FCW）为频率合成分频比控制指令。这种结构在稳定度、多样性和

36、适应性方面是非常流行、优良的。同时，寄生噪音是比其他的频率合成器要小。它需要较长的捕获时间来跳变为一个新的频率，因而切换速度低。如果当前频率与生成频率的间隔增加时，系统切换时间也增加了。DH-PLL频率合成器如图3所示。图3.采用数字查表（DLT）的DH-PLL。DLT开环结构和DAC组合成传统的锁相环闭环结构。在传统锁相环中,输出的低频电压反馈到压控振荡器。相反,每当FCW改变，DAC输出电压的总和与低频输出电压一起驱动压控振荡器。因此,与传统的锁相环不同，每当FCW更新时，该锁相环的DAC能输出电压的稳定的驱动压，所以,高速频率切换就可以实现。但是,在进行一个新频率合成时，DH-PLL有一

37、个严重的相位变化的问题。如图4中所示,超调量和建立时间有一种互为消长关系,因为FCW更新后，可编程除法器的输出漂移到另一个值,尽管系统参数的是预先优化的。所以,它需要较长的稳定时间，切换速度也降低了。鉴相器的输入为图4中所示的，号波形，是低通滤波器（LF）的控制电压。因此,在FCW更新前波形之间的关系是固定的。图4 DH-PLL工作信号但是,如果触发了一个新FCW,波形将在出乎意料的位置下降到低电平状态(“0”）,这意味着LF的电压开始发生变化。虽然DAC输出稳定的电压,但是当进行一个新的频率合成时会出现超调现象,因而稳定过程需要较长时间。与传统的锁相环相似,因为更宽的频率合成间距，超调量和稳

38、定时间变化很大。为了克服这一问题,我们另外设计了一种新的定时同步电路,完整的DH-PLL结构如图5所示。图5 新提出的DH-PLL框图。 三 仿真结果与讨论在本文中,表1的参数和表2中的步骤是用来检验我们提出了DH-PLL的电路结构的切换功能。FCW是分频比。图9和10是计算机电路模拟的结果。分频比是8bit的2进制数，FCW变化率为1/ms。分频比的变化范围应该控制在VCO的线性范围内。在图10中，上面的波形VCO的输入驱动电压，下面的波形是DAC的输出电压。如图10所示，因为鉴相器的输入与参考输入信号同步，与可编程除法器对VCO输出的计算值多少无关，所以该系统在频率合成过渡过程中超调量很小

39、，稳定时间较小。DAC在初始状态的输出电压是0V。因此,DAC和环路滤波器的输出电压相加后，驱动压控振荡器,这样就可以获得所需的频率。显然，在频率切换阶段，该系统的VCO的输入驱动电压是不同传统PLL的闭环结构的。一旦FCW改变，VCO的输入将会随着DAC输出改变而迅速改变，在短时间内跳变到一个稳定的驱动电压状态。根据以上结果,表明DHPLL具有超高速切换功能。而且,可以把我们提出的DLT替代组件与传统的ROM类型DLT在电路的复杂性方面进行比较。表1 仿真参数表2仿真过程图10压控振荡器驱动电压波形、DAC输出电压四 结论本文提出了一种使用简单的数字逻辑电路代替ROM型(DLT)的DH-PL

40、L合成器，以克服电路复杂度和传统DH-PLL的功耗。事实上,数字查找表(DLT)组件是一种硬件复杂度负担而且需要很长的访问时间使切换速度下降。此外,有一个必要条件,第一个频率控制字在初始操作时应该是一致的。同时,我们提出的电路结构解决了这个必要条件和计算机仿真结果也证实了。与传统的DH-PLL相比，硬件复杂度和功耗下降到大约28%。我们提出的这个DH-PLL结构的频率合成器可用于快速跳频系统、电子和通信系统。参考文献【1】El-Ela，M.A ，国家遥感中心99 第16届全国论文，pp.23-25 1999年2月。【2】H. G. Ryu, Y. Y. Kim, H. M. Yu and S. B. Ryu,，IEEE消费电子会报,Vol.47,NO.1，2001年2月。【3】Fouzar, Y. , Sawan, M. , Savaria, Y. ,IACAS 2000 日内瓦。2000年的IEEE国际电路与系统学术研讨会,Vol.2,pp.253-256,2000年5月。【4】David M. Materna，军事通讯联盟,军事通讯 95,会议记录，IEEE,Vol.2，pp 752-759,1995年。