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1、Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAMDRAM工作原理工作原理 DRAMDRAM工作原理工作原理Ramaxel Technology LimitedRamaxel Technology LimitedConfidential Dynamic Random Access Memory Each cell is a capacitor + a transistor Very small size SRAM uses six transistors per cell Divided into banks
2、, rows & columns Each bank can be independently controlledDRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMain MemoryEverything that happens in the computer is resident in main memoryCapacity: around 100 Mbyte to 100 Gbyte Random access Typical access time is 10- 100 nanosecondsW
3、hy DRAM for Main Memory ? Cost effective (small chip area than SRAM) High Speed(than HDD, flash) High Density(Gbyte) Mass Production Main memoryRamaxel Technology LimitedRamaxel Technology LimitedConfidentialNotation: K, M, G In standard scientific nomenclature, the metricmodifiers K, M, and G to re
4、fer to factors of 1,000,1,000,000 and 1,000,000,000 respectively. Computer engineers have adopted K as thesymbol for a factor of 1,024 (210 ) K: 1,024 (210 ) M: 1,048,576 (220 ) G: 1,073,741,824 (230 ) DRAM density 256M-bit 512M-bitRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM
5、 DensityRamaxel Technology LimitedRamaxel Technology LimitedConfidentialWhat is a DRAM? DRAM stands for Dynamic Random Access Memory. Random access refers to the ability to access any of the information within the DRAM in random order. Dynamic refers to temporary or transient data storage.Data store
6、d in dynamic memories naturally decays over time.Therefore, DRAM need periodic refresh operation to prevent data loss.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMemory: DRAM position Semiconductor memory device ROM: Non volatile Mask ROM EPROM EEPROM Flash NAND: low speed, high
7、density NOR: high speed, low density RAM: Volatile DRAM: Dynamic Random Access Memory SRAM: Static Random Access Memory Pseudo SRAMRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Trend : Future High Speed- DDR(333MHz500MHz), DDR2(533800Mbps), DDR3(8001600Mbps)- Skew-delay minimi
8、zed circuit/logic : post-charge logic, wave-pipelining- New Architecture : multi-bank structure, high speed Interface Low Power- 5.5V = 3.3V(sdr) = 2.5V(ddr) = 1.8V(ddr2) = 1.5v (ddr3) = 1.2v?- Small voltage swing I/O interface : LVTTL to SSTL, open drain- Low Power DRAM(PASR, TCSR, DPD) High Densit
9、y- Memory density: 32MB = 64MB = . 1GB = 2GB = 4GB- application expansion : mobile, memory DB for shock (than HDD)- Process shrink :145nm(03) =120nm(04) = 100nm = 90nm = 80nm Other Trends- Cost Effectiveness, Technical Compatibility, Stability, Environment. ReliabilityRamaxel Technology LimitedRamax
10、el Technology LimitedConfidentialStatic RAM SRAM Basic storage element is a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive power No need for a periodic refreshing signal or a clock Used in system cache Fastest memory, but expensiveSRAM ElementEnable Lin
11、e/Bit LineBit LineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDynamic RAM DRAM Denser type of memory Made up of one-transistor (1-T) memory cell which consists of a single access transistor and a capacitor Cheaper than SRAM Used in main memory More complicated addressing schemeDR
12、AM CellWord LineBit LineRamaxel Technology LimitedRamaxel Technology LimitedConfidentialRefresh in DRAMsCapacitor leaks over time, the DRAM must be “REFRESHED”. DRAM CellWord LineBit LineCapacitance LeakageRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSRAM vs. DRAMRamaxel Technolog
13、y LimitedRamaxel Technology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Lead Frame and Wire bondingRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidential SDRAM has t
14、he multi bank architecture. Conventional DRAM was product that have single bank architecture. The bank is independent active. memory array have independent internal data bus that have same width as external data bus. Every bank can be activating with interleaving manner. Another bank can be activate
15、d while 1st bank being accessed. (Burst read or write)Multi Bank ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Multi Bank ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Single Bank ArchitectureRamaxel Technology LimitedRamaxel Tech
16、nology LimitedConfidentialRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Block Diagram(1)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Block Diagram(2)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Core ArchitectureRamaxel Technology
17、 LimitedRamaxel Technology LimitedConfidentialDRAM AddressRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Core ArchitectureRamaxel Technology LimitedRamaxel Technology LimitedConfidential16bit DRAM CoreRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Data Pat
18、hRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM 1T-1C structureRamaxel Technology LimitedRamaxel Technology LimitedConfidentialuRAS: row address strobeuCAS: column address strobeuWE: write enableuAddress: code to select memory cell locationuDQ (I/O): bidirectional channel to tr
19、ansfer and receive datauDRAM cell: storage element to store binary data bituRefresh: the action to keep data from leakageuActive: sense data from DRAM celluPre charge: standby stateDRAM Key wordRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM cell array consist of so many cells.O
20、ne transistor & One capacitorSmall sense amplifierLow input gain from charge sharingCS : Small storage capacitor: 25fFCBL : Large parasitic capacitor: over 100fFVc: Storage voltageVCP : half Vc for plate biasVBLP : half Vc for BL pre charge bias(initial bias)DRAM CellRamaxel Technology LimitedRamaxe
21、l Technology LimitedConfidentialDRAM Array Overview Simplified ExampleBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WO
22、RDLINE 3DATA BITRamaxel Technology LimitedRamaxel Technology LimitedConfidentialActivating a Row Activating a Row Must be done before a read or write Just latch the row address and turn on a single wordlineBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS
23、 A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITRamaxel Technology LimitedRamaxel Technology LimitedConfidentialWriting Writing A row must be active Select the column address Drive the data throug
24、h the column mux Stores the charge on a single capacitorBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINECOLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA B
25、ITZEROONERamaxel Technology LimitedRamaxel Technology LimitedConfidentialReading Reading A row must be active Select the column address The value in the sense-amplifier is driven back outBITLINE 0BITLINE 0#BITLINE 1BITLINE 1#BITLINE 2BITLINE 2#BITLINE 3BITLINE 3#ROW DECODERSELECTS A SINGLE WORDLINEC
26、OLUMN MULTIPLEXER CONNECTS A SINGLE BITLINECOLUMNADDRESSROWADDRPRECHARGE CONTROL LINEWORDLINE 0WORDLINE 1WORDLINE 2WORDLINE 3DATA BITZEROONERamaxel Technology LimitedRamaxel Technology LimitedConfidentialThe Sense-Amplifier Sense-Amplifier A pair of cross-coupled inverters Basically an SRAM element
27、Weaker than the column mux Write data will “outmuscle” the sense-amplifier Keeps the data at full levelBITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialPrechargePrecharge Inactive state (no wordlines active) Precharge control line high Tie
28、s the two sides of the sense-amp together This makes the bitlines stay at VDD/2 Only stable as long as the precharge control line is highotherwise this is unstable! No capacitors connectedBITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialAc
29、tivation RevisitedActivation Turn off the precharge control line Makes the sense-amp unstableit wants to go to either 0 or 1 instead of staying at VDD/2 A very very very short time later, turn on the wordline of the row to be activated. Couples the capacitor onto the bitlines This “tips” the bitline
30、s to hold the stored value. The sense-amp amplifies the capacitor back to full value. (hence the name!)BITLINEBITLINE #WORDLINEPRECHARGE CONTROL LINERamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Refresh Because the stored memory value is stored on a capacitor (that has resisti
31、ve leakage), the memory is constantly “forgetting” its contents. Eventually, the charge on the capacitor wont be enough to tip the sense-amp in the right direction. But, activating a row restores the cells on that row to their full value. There is an explicit refresh command that just activates and
32、immediately deactivates a row. The DRAM has an internal counter that contains the next row to be refreshed and increments every time a refresh command is issued.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Refresh Data Retention Time DRAM Cell consists of capacitance which ha
33、s leakage as time Retention time is period for maintaining its data especially 1 data Usually, DRAM Cell refresh period is 64ms Refresh Timing tREF : Real cell retention time (Device characteristic), ex) 90ms(Hot) tRFC : Refresh command operating time, ex) 75ns Refresh Spec. Burst Refresh : 64ms Dis
34、tribute refresh- 128Mb device (12 Row address) : 64ms / 4K = 15.6us- 256Mb device (13 Row address) : 64ms / 8K = 7.8usRamaxel Technology LimitedRamaxel Technology LimitedConfidentialAUTO Refresh When this command is input from the IDLE state, the synchronous DRAM starts autorefresh operation. During
35、 the auto-refresh operation, refresh address and bank select address are generated inside the Synchronous DRAM. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192times are required to refresh the entire memory. Before executing the auto-refresh command, all the
36、bank must be IDLE state. In addition, since the Precharge for all bank is automatically performed after auto-refresh, no Precharge command is required after auto-refresh.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialSelf Refresh Self-Refresh EntrySELF : When this command is input d
37、uring the IDLE state, the Synchronous DRAM starts self-refresh operation. After the execution of this command, selfrefresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Self-Refresh ExitSELFX : When this command
38、 is executed during self-refresh mode, the Sync DRAM can exit from self-refresh mode. After exiting from self-refresh mode, the Sync DRAM enters the IDLE state., no Precharge command is required after auto-refresh.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialMode Register Special
39、command to initialize the DRAM Burst length Interleaving CAS Latency (read command to read data in clocks) For DDR, DLL reset is also hereRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMRS Block DiagramRamaxel Technology LimitedRamaxel Technology LimitedConfidentialMode Register Bec
40、ause the stored memory value is stored on aRamaxel Technology LimitedRamaxel Technology LimitedConfidentialExtended Mode Register Special command to initialize DDR DRAM DDR onlydont use for SDR DLL Enable Drive StrengthRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDRAM Interface Co
41、mmand Signals CAS#, RAS#, WE#, CS# CS# + CAS# = Read CS# + WE# + CAS# = Write CS# + RAS# + CAS# = Refresh CS# + RAS# = Activate CS# + WE# = Burst Stop CS# + WE# + RAS# = Precharge CS# + WE# + CAS# + RAS# = MRS or EMRS All others: NOP Other signals: CLK, DATA , DQSRamaxel Technology LimitedRamaxel Te
42、chnology LimitedConfidentialDRAM Interface All signals go from the host to the memory except DQS and data which are bi-directional.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialRead Cycle Typical Read Cycle Burst Length 4 CAS Latency = 3Setup TimeHold TimeCAS LatencyCLKCAS#DQSDATAD
43、QS delayed to simulate what the NV controller does.Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialWrite Cycle Typical Write Cycle Burst Length 4 Write latency is always zeroSetup TimeHold TimeCLKCAS#DQSDATARamaxel Technology LimitedRamaxel Technology LimitedConfidentialData Clocking
44、 CLK is always driven by the host DQS is driven by whoever is driving the data NV chip drives on write cycles Memory chip drives on read cycles This scheme is called “source-synchronous clocking” Eliminates a lot of the timing headaches from SDR Adds marginRamaxel Technology LimitedRamaxel Technolog
45、y LimitedConfidentialLatencies All kinds Activate to Precharge Last write data to precharge Activate to Read Activate to Write Refresh cycle time Refresh interval Minimum row active time Yadda yadda yadda Controlled by PFB_TIMING0, PFB_TIMING1, PFB_TIMING2Ramaxel Technology LimitedRamaxel Technology
46、 LimitedConfidentialWrite CycleRamaxel Technology LimitedRamaxel Technology LimitedConfidentialDLLsA DLL is a Delay-Locked Loop No transistor can switch in zero time, so there will be a delay between clock and DQS on reads But, it would make it easier if DQS was always in phase with clock. DLL-off c
47、lock-DQS delay not in the spec Varies between memory vendorsRe-creates a delayed version of its input clock Keeps DQS on reads aligned with clocks Its an analog circuit and is sensitive to noise Can lose lock on the input clock if the signal is not clean or the DLL power supply is noisy.Ramaxel Tech
48、nology LimitedRamaxel Technology LimitedConfidentialDLLs DLL on DLL offCLKDQSDATACAS#CLKDQSDATACAS#DQS delayed to simulate what the NV controller does.DQS delayed to simulate what the NV controller does.Ramaxel Technology LimitedRamaxel Technology LimitedConfidential tAA, tAC, tOH tRCD, tRP Set-up /
49、 Hold time Vih, Vil Voh, Vol Ioh, IolTiming ParametersRamaxel Technology LimitedRamaxel Technology LimitedConfidentialSDRAM Timing DiagramRamaxel Technology LimitedRamaxel Technology LimitedConfidentialtAA ,tAC, tOH(SDRAM)Ramaxel Technology LimitedRamaxel Technology LimitedConfidentialSetup/hold tim
50、e Timing for latching data in Input buffer CLK rising edge is strobe for data ( SDRAM ) DQS rising & falling edge is strobe for data(DDR SDRAM) During Setup & time, there is no abnormal signal allowedRamaxel Technology LimitedRamaxel Technology LimitedConfidentialVIH/VILRamaxel Technology LimitedRam