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1、2.1 CMOS制造工艺流程简介制造工艺流程简介 We will describe a modern CMOS process flow.Process described here requires 16 masks and 100 process steps.1第二第二章章 CMOS制备基本流程制备基本流程Stages of IC Fabrication2 In the simplest CMOS technologies,we need to realize simply NMOS and PMOS transistors for circuits like those illustra
2、ted below.CMOS Digital Gates反相电路或非门：同时输入低电平时才能获得高电平输出3PMOS and NMOSwafer cross section after fabrication2-Level Metal CMOS两层互连布线的两层互连布线的CMOS4有源器件（MOS、BJT等类似器件），必须在外加适当的偏置电压情况下，器件才能正常工作。对于MOS管，有源区分为源区和漏区，在进行互联之前，两者没有差别。Choosing a SubstrateActive RegionN and P WellGateTip or ExtensionSource and DrainC
3、ontact and Local InterconnectMultilevel MetalizationProcessing Phases51 m Photoresist40 nm SiO2Choose the substrate(type,orientation,resistivity,wafer size)Initial processing:-Wafer cleaning-thermal oxidation,H2O(40 nm,15 min.900C)-nitride LPCVD(低压化学气相沉积)(80 nm 800C)Substrate selection:-moderately h
4、igh resistivity(25-50 ohm-cm)-(100)orientation-P-type.80 nm Si3N4Choosing a SubstrateSi,(100),P Type,2550cm1st Mask Photoresist spinning and baking 100C(0.5-1.0 m)62.2 有源区的形成有源区的形成 Photolithography -Mask#1 pattern alignment and UV exposure -Rinse away non-pattern PR -Dry etch the Nitride layer -Plas
5、ma etch with Fluorine CF4 or NF4 Plasma -Strip Photoresist(H2SO4或或O2 plasma)Active Area Definition(主主动区区)SiO2Si3N4Photoresist7 Wet Oxide(thick SiO2)-H2O(500 nm,90 min.1000C)Strip Nitride layer-Phosophoric acid(磷酸)or plasma etch，选择性问题Field Oxide Growth-LOCOS:Local Oxidation of Silicon(局部硅氧化工艺)SiO2Si3
6、N4 薄的SiO2层，厚的Si3N4层，避免鸟喙(birds beak)的影响8 场区:很厚的氧化层，位于芯片上不做晶体管、电极接触的区域，可以起到隔离晶体管的作用。Photolithography(套刻套刻)-Mask#2 pattern alignment and UV exposure Ion Implantation 离子注入离子注入-B+ion bombardment-Penetrate thin SiO2 and field SiO2 -反反型型：半导体表表面面的少数载流子浓度等于体内的多数载流子浓度时，半导体表面开始反型。-150-200 keV for 1013cm-2-Imp
7、lantation Energy and total dose adjusted for depth and concentrationP-well Fabrication Strip Photoresist-Rinse away non-pattern PR2.3 N阱和阱和P阱的形成阱的形成SiO2Photoresist9 Ion Implantation-P+ion bombardment-Penetrate thin SiO2 and fieldSiO2-300-400 keV for 1013cm-2-Implantation Energy andtotal dose adjuste
8、d fordepth and concentration Strip PhotoresistN-well Fabrication Photolithography -Mask#3 pattern alignment and UV exposure -Rinse away non-pattern PR10 Thermal Anneal (热退火退火)-Repair crystal lattice structure damage due to implantation Dry Furnace (N2 ambient，防止氧化层生成)-Anneal 30 min 800C or RTA(快速热退火
9、)10 sec 1000C-Drive-in 4-6 hours 1000 C-1100 CThermal Anneal and Diffusion N and P Drive-in (扩散推散推进)-Thermal diffusion of dopant to shallower than desired depth -Drive-in is a cumulative process!11 Photolithography -Mask#4 pattern alignment and UV exposure -Rinse away non-pattern PR-B+ion bombardmen
10、t-50-75keV for 1-5 1012cm-2-Implantation Energy andtotal dose adjusted fordepth and concentration Strip PhotoresistThreshold Adjustment,P-type NMOS Ion Implantation2.4 栅电极的制备栅电极的制备开启开启电压调电压调整整12调整之前P阱的掺杂浓度调整时的注入剂量Threshold Adjustment,N-type PMOS Photolithography -Mask#5 pattern alignment and UV expo
11、sure -Rinse away non-pattern PR-As+ion bombardment-75-100keV for 1-5 1012cm-2-Implantation Energy andtotal dose adjusted fordepth and concentration Strip Photoresist Ion Implantation13 Remove existing gate region oxide Furnace Steps-Thermal Anneal-Oxide growth 3-5 nm -O2 ambient -0.5-1 hour 800C Gat
12、e Oxide Growth 栅极氧极氧化化层生生长-HF etch，具有良好的选择性 -Dry Furnace(N2 ambient)-30 min 800C14 LPCVD Deposition of Si -Silane 硅烷 Amorphous or polycrystallinesilicon layer results Ion Implantation-P+or As+(N+)implant dopesthe poly(typically 5 1015 cm-2)Polysilicon Gate Deposition 0.3-0.5 umSiO2多晶硅薄膜15热分解 Photoli
13、thography -Mask#6 pattern alignment and UV exposure Plasma Etch-Anisotropic etch 各向异性蚀刻-Vertical etch rate high-Lateral etch rate lowGate Patterning（栅极极的的图形化形化）-Rinse away non-pattern PR Clorine(氯)or Bromine(溴溴)based for SiO2 selectivity16目标：NMOS器件中的N-注入区PMOS器件中的P-注入区多晶硅栅的两侧形成侧壁隔离层的薄氧化层2.5 前端或延伸区前端或
14、延伸区(LDD)的形成的形成17LDD:Lightly Doped Drain(轻掺杂漏)Reduce short channel effects due to gate voltage magnitudes and electric fields Source and Drain must be layered as NMOS:N+N-P or PMOS:P+P-NExtension(LDD)Formation NMOS Photolithography -Mask#7 pattern alignment and UV exposure -Rinse away non-pattern PR-
15、P+ion bombardment-50keV for 5 1013cm-2 Strip Photoresist Ion Implantation18 Photolithography Mask#8 pattern alignmentand UV exposure Rinse away non-pattern PR Ion Implantation B+ion bombardment 50 keV for 5 1013cm-2 Strip PhotoresistExtension(LDD)Formation PMOS19SiO2 隔离介隔离介质层 CVD or LPCVD Deposition
16、 of SiO2 Silane and OxygenOr 0.5 um Provides spacing between gate and source-drain.SiO2 Spacer Deposition20 Photolithography Mask#6 oversized patternalignment and UV exposure Rinse away non-pattern PR Vertical etch rate high Lateral etch rate low Strip PhotoresistAnisotropic Spacer Etch Plasma Etch
17、Anisotropic etch Flourine based21 Screen Oxide Growth Thin SiO2 layer 10 nm to scatter the implanted ions Photolithography Mask#9 pattern alignmentand UV exposure Rinse away non-pattern PR Ion Implantation As+ion bombardment 75 keV for 2-4 1015cm-2 Strip PhotoresistNMOS Source and Drain Implant2.6 源
18、漏区的形成源漏区的形成Arsenic Reduce channeling22 Photolithography Mask#10 pattern alignmentand UV exposure Rinse away non-pattern PR Ion Implantation B+ion bombardment 5-10 keV for 1-3 1015cm-2 Strip PhotoresistPMOS Source and Drain Implant23 N+and P+Drive-in Thermal diffusion of dopant to shallower than desi
19、red depthDrive-in is a cumulative process!Dry Furnace(N2 ambient)Anneal 30 min 900C or RTA 60 sec 1000 C-1050 CTransient Enhanced Diffusion(TED 瞬态增强扩散)Higher than normal diffusivity due to crystal damageThermal Annealing Thermal Anneal Repair crystal lattice structure damage due to implantation242.7
20、 接触与局部互联的形成接触与局部互联的形成 Contacts and Interconnects Titanium sputtering local contacts Conformal Coat with SiO2 Planarization Tungsten Plug vias Aluminum Metal Deposition Repeat Coat Planarize Plug Metal deposition25 HF etch to remove thin SiO2 Remove screen oxide from drain,source and ploy gate region
21、s Dip(浸)for a few seconds with HFContact OpeningsLDD and Sidewall structure NMOS:Lateral N+N-P N-N+PMOS:Lateral P+P-N P-P+26 Titanium Deposition Ti is deposited by sputtering(typically 100 nm).Ti target hit with Ar+ions in a vacuum chamber The Ti is reacted in an N2 ambient Forms TiSi2 and TiN(typic
22、ally 1 min 600-700 C).TiSi2 has excellent contact characteristics(良好的导体)TiN does not,but can be used for local wiring(导电材料，短程互连布线)TiSi2TiN27 Photolithography Mask#11 pattern alignment and UV exposure Rinse away non-pattern PR TiN etch NH4OH:H2O2:H2O(1:1:5)Strip PhotoresistLocal TiN Interconnect Ther
23、mal Treat in Ar 减小电阻 1 min 800 C28用用TiN作作为为局部互局部互连连引引线线 Conformal layer of SiO2 is deposited by CVD or LPCVD(typically 1 m)PSG(磷硅玻璃)or BPSG(硼磷硅玻璃)磷：Surface passivation(表面钝化)硼：Glass reflow for partial planarization(加热，令表面平整)Chemical Mechanical Polishing (CMP 化学机械抛光)Planarize the wafer surface 平坦化 Pol
24、ish with high pH silica slurry(硅酸盐研磨浆料)Conformal Coat and Planarize2.8 多层金属互连的形成多层金属互连的形成SiO229 表面不平坦带来很多问题,两种解决方法：Photolithography Mask#12 pattern alignment and UV exposure Rinse away non-pattern PR SiO2 plasma etch Anisotropic etch Strip PhotoresistVias to 1st Metal30 选择第一层金属布线需要与下层器件结构形成连接的接触孔位置
25、接触孔形成 Via Deposition Tungsten Plugs(插插头)TiN or Ti/TiN barrier layer 粘结层/阻挡层，增强金属与SiO2的粘附性 Sputtering or CVD(few tens of nm)CVD Tungsten(W)Chemical Mechanical Polishing(CMP)Planarize the wafer surface Polish with high pH silica slurry31 Etch Contact Holes(接触孔的接触孔的蚀蚀刻刻)or Line Trenches(沟道沟道)Fill etche
26、d regions(蚀蚀刻区的填充刻区的填充)Planarize(平坦化平坦化)CMP process Also removes material that“overflowed holes or trenches”Damascene Process 大大马士革士革镶嵌工嵌工艺32大大马马士革士革镶镶嵌工嵌工艺艺包括：包括：Strip PhotoresistMetal#1 Deposition第一层金属布线第一层金属布线 Photolithography Mask#13 pattern alignment and UV exposure Rinse away non-pattern PR An
27、isotropic plasma etch33SiO2Al光刻胶 Sputtered Aluminum Al with small amounts of Si and Cu -Cu reduces electromigration 避免电迁移现象带来的断路 -Si 降低接触电阻 Multiple Metal Layers Deposits Oxide Layer CMP Photolithography Mask#14 Etch Vias Deposit via material CMP Deposit Next Metal Layer Photolithography Mask#15 Fin
28、al passivation layer of Si3N4 is deposited by PECVD and patterned with Mask#16.防止Na+、K+污染和封装中的机械损伤 Final anneal and alloy in forming gas(10%H2 in N2)30min 400-450 C 形成良好的欧姆接触，降低Si/SiO2界面的电荷34SiO2WTiNSi3N4或SiO2Intel processor chip52MB SRAM chips on a 12”wafer Photos of state-of-the-art CMOS chips(fro
29、m Intel website).90 nm technology.35Summary of Key ideas This chapter serves as an introduction to CMOS technology.It provides a perspective on how individual technologies like oxidation and ion implantation are actually used.There are many variations on CMOS process flows used in industry.The proce
30、ss described here is intended to be representative,although it is simplified compared to many current process flows.Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologies,their actual use is complicated by the fact that IC manufacturing consists of many sequential steps,each of which must integrate together to make the whole process flow work in manufacturing.36作作业：MEMS 器件制备器件制备最早的最早的MEMS执执行器之一：静行器之一：静电驱动电驱动的微的微马马达达37