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1、VHDL双语教学第2章Agendan nDesign ExamplenBasic Language FrameworkMajority Voter CircuitnOutput 1 of there is more 1s than 0snOutput 0 of there is more 0s than 1s多数表决器SchematicCPLDVHDL Descriptionlibrary ieee;use ieee.std_logic_1164.all;-entity XYZ is -Can put anything after the-port (A1,A2,A3 :in std_logi
2、c;F :out std_logic);end XYZ;-architecture XYZ _arch of XYZ isbegin F=(A1 and A2)or(A2 and A3)or(A1 and A3);end XYZ_arch;ABCA1A2A3FA1A2A3FFileXYZ.VHDSimulationDownload to ChipsAgendan nDesign Examplen nBasic Language FrameworkXYZ Clock DiagramXYZ(Entity)ABCFXYZ_arch1(Architecture)XYZ.VHD (1)data flow
3、libraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;-CommentsF:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginF=(AandB)or(BandC)or(CandA);endXYZ_arch;XYZ.VHD (2)data flowlibraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-arc
4、hitectureXYZ_archofXYZisbeginF=1when(A=1)and(B=1)else1when(B=1)and(C=1)else1when(A=1)and(C=1)else0;endXYZ_arch;XYZ.VHD (3)behaviorallibraryieee;useieee.std_logic_1164.all;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZisbeginprocess(A,B,C)beginif(A=1)and(B=1)then
5、F=1;elsif(B=1)and(C=1)thenF=1;elsif(A=1)and(C=1)thenF=1;elseF=0;endif;endprocess;endXYZ_arch;XYZ.VHD (4)structurallibraryieee;useieee.std_logic_1164.all;libraryaltera;usealtera.maxplus2.ALL;-entityXYZisport(A,B,C:instd_logic;F:outstd_logic);endXYZ;-architectureXYZ_archofXYZissignalF1,F2,F3:std_logic
6、;beginU1:and2portmap(A,C,F1);U2:and2portmap(A,B,F2);U3:and2portmap(B,C,F3);F=F1orF2orF3;endXYZ_arch;XYZ All in One Block DiagramXYZ(Entity)ABCFXYZ_arch1XYZ_arch2XYZ_arch3XYZ_arch4(Architecture)XYZ.VHD (All in One)library ieee;use ieee.std_logic_1164.all;LIBRARY altera;USE altera.maxplus2.ALL;-*entit
7、y XYZ is port (A,B,C :in std_logic;F :out std_logic );end XYZ;-*architecture XYZ_arch1 of XYZ isbegin F=(A and B)or(B and C)or(C and A);end XYZ_arch1;-architecture XYZ_arch2 of XYZ isbegin F=1 when(A=1)and(B=1)else 1 when(B=1)and(C=1)else 1 when(A=1)and(C=1)else 0;end XYZ_arch2;-architecture XYZ_arc
8、h3 of XYZ isbegin process(A,B,C)begin if(A=1)and(B=1)then F=1;elsif(B=1)and(C=1)then F=1;elsif(A=1)and(C=1)then F=1;else F=0;end if;end process;end XYZ_arch3;-architecture XYZ_arch4 of XYZ is signal F1,F2,F3:std_logic;begin U1:and2 port map(A,C,F1);U2:and2 port map(A,B,F2);U3:and2 port map(B,C,F3);F
9、=F1 or F2 or F3;end XYZ_arch4;-XXYYZZ XXYYZZXYZMY_PACKAGE.VHDlibraryieee;useieee.std_logic_1164.all;-packagemy_packageiscomponentXYZisport(A,B,C:instd_logic;F:outstd_logic);endcomponent;endmy_package;XXYYZZ.VHDlibraryieee;useieee.std_logic_1164.all;librarywork;usework.my_package.all;-entityXXYYZZisport(A1,A2,B1,B2,C1,C2:instd_logic;F:outstd_logic);endXXYYZZ;-architectureXXYYZZ_archofXXYYZZissignalF1,F2:std_logic;beginG1:XYZportmap(A1,B1,C1,F1);G2:XYZportmap(A2,B2,C2,F2);F=F1orF2;endXXYYZZ_arch;