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1、VHDLSimulation & Synthesis第一页，共三十三页。AgendaOther Features in VHDLAssertFunction OverloadingFILE IO第二页，共三十三页。Generate Example (1)ram32 : ram_0 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(7 downto 0); ram_1 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(15 downto 8); ram_
2、2 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(23 downto 16); ram_3 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(31 downto 24);end generate ram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bit addr8-bit addr8-bit addr8-bit addr第三页，共三十三页。Generate Exampl
3、e (2) ram32 : i 3 downto 0 ram :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(8*i+7 downto 8*i); ram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bit addr8-bit addr8-bit addr8-bit addr第四页，共三十三页。GenerateLabel: ParameterName Range ConcurrentStatements. Label;Label: Condit
4、ion ConcurrentStatements. Label; 第五页，共三十三页。Generate Example (3)Addera(0)a(1)a(2)a(wid-1)b(0)b(1)b(2)b(wid-1)sum(0)sum(1)sum(2)sum(wid-1)carryHAFAFAFAa(0)b(0)c_in(1)a(1)b(1) c_in(2) a(2)b(2)c_in(3)c_in(win-1) a(wid-1)b(wid-1)sum(0)sum(1)sum(2)sum(wid-1)carry第六页，共三十三页。Generate Example (4)adder : i 0 w
5、id-1 ls_bit : i = 0 ls_cell : HA port map (a(0), b(0), sum(0), c_in(1); lsbit;middle_bit : i 0 and i wid-1 middle_cell : FA port map (a(i), b(i), c_in(i), sum(i), c_in(i+1); middle_bit;ms_bit : i = wid-1 ms_cell : FA port map (a(i), b(i), c_in(i), sum(i), carry); ms_bit; adder; HAFAFAFAa(0)b(0)c_in(
6、1)a(1)b(1) c_in(2) a(2)b(2)c_in(3)c_in(win-1) a(wid-1)b(wid-1)sum(0)sum(1)sum(2)sum(wid-1)carry第七页，共三十三页。AgendaGenerateFunction OverloadingFILE IO第八页，共三十三页。AssertDefinitionLabel: Condition report StringExpression severity Expression;Note!lThe default string for clause is “Assertion violation”lThe de
7、fault string for clause is “ERROR”第九页，共三十三页。Concurrent Assertions & Concurrent Procedure CallsLabel : condition error_string severity_value;Label : condition error_string severity_value; sensitivity_clause ; Label; concurrent assertionsconcurrent procedure calls第十页，共三十三页。Assert Example (1) not (Rese
8、t = 0 and Set = 0) R-S conflict Failure;第十一页，共三十三页。Assert Example (2)第十二页，共三十三页。Severity_leveltype is (, , , ); (In standard.vhd)第十三页，共三十三页。AgendaGenerateAssertFILE IO第十四页，共三十三页。Function OverloadingVHDL allows two subprograms to have the same name, provided the number or base types of parameters dif
9、fers 第十五页，共三十三页。Function Overloading (Example 1)function Foo(value : bit) return boolean;function Foo(value : std_logic) return boolean; 第十六页，共三十三页。Function Overloading (Example 2)function + (arg1, arg2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;function + (L, R: UNSIGNED) return UNSIGNED;function
10、+ (L, R: SIGNED) return SIGNED;第十七页，共三十三页。Function Overloading (Example 3) FUNCTION + (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS CONSTANT ml : INTEGER := maximum(arg1length,arg2length); VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml); VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml); VARIABLE res : ST
11、D_LOGIC_VECTOR(1 TO ml); VARIABLE carry : STD_LOGIC := 0; VARIABLE a,b,s1 : STD_LOGIC; - Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD ; BEGIN lt := zxt( arg1, ml ); rt := zxt( arg2, ml ); FOR i IN resreverse_range LOOP a := lt(i); b := r
12、t(i); s1 := a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END;FUNCTION + (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS CONSTANT ml : INTEGER := maximum(arg1length,arg2length); VARIABLE lt : UNSIGNED(1 TO ml); VARIABLE rt : UNSIGNED(1 TO ml); VARIABLE res : UNSIG
13、NED(1 TO ml); VARIABLE carry : STD_LOGIC := 0; VARIABLE a,b,s1 : STD_LOGIC; - Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD ; BEGIN lt := zxt( arg1, ml ); rt := zxt( arg2, ml ); FOR i IN resreverse_range LOOP a := lt(i); b := rt(i); s1 :=
14、 a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END;第十八页，共三十三页。Function Overloading (Example 4)function (a, b : byte) return byte isbegin return int_to_byte(byte_to_int(a) + byte_to_int(b);end +; X1000_0010 X0000_FFD0 (X1000_0010, X0000_FFD0) 第十九页，共三十三页。Agen
15、daGenerateAssertFunction OverloadinglBinary File第二十页，共三十三页。Read/Write Text File12123122341Awfe011100010-Disk File1001011011Line variableReadLine()Read()Data Object12123122341Awfe011100010-Disk File1001011011Line variableWriteLine()Write()Data ObjectRead From Text FileWrite To Text File第二十一页，共三十三页。Re
16、ad/Write Text File StepsStep 1 Define user data object, DataObjStep 2 Define Line object, LineObjvariable LineObj: line; Step 2 Define TextFile object, FileObj file FileObject: text is in FileName; file FileObject: text is out FileName; Step 4 Read/Write DatalReadreadLine(FileObj, LineObj);read(Line
17、Obj, DataObj); lWriteWrite(LineObj, DataObj);WriteLine(FileObj, LineObj);第二十二页，共三十三页。Read/Write Text File (Example)library ieee;use ieee.std_logic_1164.all;use std.textio.all;entity text_file_read isend text_file_read;architecture text_file_read_a of text_file_read isbegin process variable bv: bit_v
18、ector(3 downto 0); variable ln_in: line; variable ln_out: line; file file_in: text is in text1.dat; file file_out: text is out text2.dat; begin loop exit when endfile(file_in); readline(file_in, ln_in); read(ln_in, bv); write(ln_out, bv); writeline(file_out, ln_out); end loop; wait; end process;end
19、text_file_read_a; 11111010text1.dat11111010text2.dat第二十三页，共三十三页。Write Text File (Example 1)library ieee;use ieee.std_logic_1164.all;use std.textio.all; entity text_file_write isend text_file_write; architecture text_file_write_a of text_file_write isbegin process variable ln: line; variable bv: bit_
20、vector(3 downto 0); file out_file: text is out text1.dat; begin bv := 1111; write(ln, bv); writeline(out_file, ln); bv := 1010; write(ln, bv); writeline(out_file, ln); wait; end process;end text_file_write_a; 11111010text1.dat第二十四页，共三十三页。Write Text File (Example 2)entity Write_File isend entity Writ
21、e_File;architecture arch_Write_File of Write_File is signal A, B, C: Bit_vector(3 downto 0);begin A = 1100; B=0110; C=0101; Monitor: process use STD.TEXTIO.all; file F: TEXT is out c:test.txt; -VHDL87 variable L: LINE; begin WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); W
22、RITE (L, C, Right, 5); WRITELINE (F, L); wait for 0 ns; WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait for 1 ns; WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L
23、); wait; end process;end architecture arch_Write_File;0 ns 0000 0000 00000 ns 1100 0110 01011 ns 1100 0110 0101 10 5 5 5第二十五页，共三十三页。AgendaGenerateAssertFunction OverloadinglText File第二十六页，共三十三页。Read/Write Binary FileStep 1 Define File Format (Store data type) DataTypeStep 2 Define user data object,
24、DataObjStep 3 Define File object, FileObjfile FileObject: DataType is in FileName ;file FileObject: DataType is out FileName;Step 4 Define data length variable, LengthStep 5 Read/Write Dataread(FileObj, DataType, Length);write(FileObj, DataObject);第二十七页，共三十三页。Write Binary Filelibrary ieee;use ieee.s
25、td_logic_1164.all;use std.textio.all; entity file_write isend file_write;architecture file_write_a of file_write is type bit_vec is file of bit_vector; file out_file: bit_vec is out F1.dat;begin process variable v: bit_vector(3 downto 0); begin v := 1101; write(out_file, v); wait for 100 ms; v := 00
26、01; write(out_file, v); wait for 100 ms; v := 1111; write(out_file, v); wait for 100 ms; wait; end process;end file_write_a; 第二十八页，共三十三页。Read/Write Binary Filearchitecture file_read_a of file_read is type bit_vec is file of bit_vector; file in_file: bit_vec is in F1.dat; file out_file: bit_vec is ou
27、t F2.dat;begin process variable v: bit_vector(3 downto 0); variable len: natural:= 1; begin loop exit when endfile(in_file); read(in_file, v, len); write(out_file, v); wait for 100 ms; end loop; wait; end process;end file_read_a; library ieee;use ieee.std_logic_1164.all;use std.textio.all; entity fi
28、le_read isend file_read;第二十九页，共三十三页。Definitions For Text File (1)package TEXTIO is - Type definitions for text I/O: type LINE is access STRING; - A LINE is a pointer to a STRING value. type TEXT is file of STRING; - A file of variable-length ASCII records. type SIDE is (RIGHT, LEFT); - For justifyin
29、g output data within fields. subtype WIDTH is NATURAL; - For specifying widths of output fields. - Standard text files: file INPUT: TEXT open READ_MODE is STD_INPUT; file OUTPUT: TEXT open WRITE_MODE is STD_OUTPUT; - Input routines for standard types: procedure READLINE (file F: TEXT; L: out LINE);
30、procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BIT); procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BIT_VECTOR); procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD:
31、 out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);第三十页，共三十三页。Definitions For Text File (2) procedure READ (L: inout LINE; VALUE: out CHARACTER); procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLE
32、AN); procedure READ (L: inout LINE; VALUE: out INTEGER); procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out REAL); procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out STRING); proce
33、dure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out TIME); - Output routines for standard types: procedure WRITELINE (file F: TEXT; L: inout LINE); procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); p
34、rocedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WID
35、TH := 0);第三十一页，共三十三页。Definitions For Text File (3) procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0); procedure WRITE (L: inou
36、t LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns); - File position predicate: -function ENDFILE (file F: TEXT) return BOOLEAN;end TEXTIO;第三十二页，共三十三页。内容(nirng)总结VHDL。a(0)a(1)a(2)。b(0)b(1)b(2)。sum(0)sum(1)sum(2)。a(0)b(0)c_in(1)。sum(1)sum(2)。end +。writeline(file_out, ln_out)第三十三页，共三十三页。