MSP430G2553库函数7794.pdf

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1、/*Standard register and bit definitions for the Texas Instruments*MSP430 microcontroller.*This file supports assembler and C development for*MSP430G2553 devices.*Texas Instruments,Version *Rev.,Setup*/#ifndef _MSP430G2553#define _MSP430G2553#define _MSP430_HEADER_VERSION_ 1062#ifdef _IAR_SYSTEMS_ICC

2、_#ifndef _SYSTEM_BUILD#pragma system_include#endif#endif#if(_TID_ 8)&0 x7F)!=0 x2b)/*0 x2b=43 dec*/#error file for use with ICC430/A430 only#endif#ifdef _IAR_SYSTEMS_ICC_#include#pragma language=extended#define DEFC(name,address)_no_init volatile unsigned char name address;#define DEFW(name,address)

3、_no_init volatile unsigned short name address;#define DEFXC volatile unsigned char#define DEFXW volatile unsigned short#endif /*_IAR_SYSTEMS_ICC_ */#ifdef _IAR_SYSTEMS_ASM_#define DEFC(name,address)sfrb name=address;#define DEFW(name,address)sfrw name=address;#endif/*_IAR_SYSTEMS_ASM_*/#ifdef _cplus

4、plus#define READ_ONLY#else#define READ_ONLY const#endif /*STANDARD BITS*/#define BIT0 (0 x0001u)#define BIT1 (0 x0002u)#define BIT2 (0 x0004u)#define BIT3 (0 x0008u)#define BIT4 (0 x0010u)#define BIT5 (0 x0020u)#define BIT6 (0 x0040u)#define BIT7 (0 x0080u)#define BIT8 (0 x0100u)#define BIT9 (0 x020

5、0u)#define BITA (0 x0400u)#define BITB (0 x0800u)#define BITC (0 x1000u)#define BITD (0 x2000u)#define BITE (0 x4000u)#define BITF (0 x8000u)/*STATUS REGISTER BITS*/#define C (0 x0001u)#define Z (0 x0002u)#define N (0 x0004u)#define V (0 x0100u)#define GIE (0 x0008u)#define CPUOFF (0 x0010u)#define

6、OSCOFF (0 x0020u)#define SCG0 (0 x0040u)#define SCG1 (0 x0080u)/*Low Power Modes coded with Bits 4-7 in SR*/#ifndef _IAR_SYSTEMS_ICC_/*Begin#defines for assembler*/#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+C

7、PUOFF)/*End#defines for assembler*/#else/*Begin#defines for C*/#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include#define LPM0 _BIS_SR(LPM0_bits)/*Enter Low Power Mode 0*/#defi

8、ne LPM0_EXIT _BIC_SR_IRQ(LPM0_bits)/*Exit Low Power Mode 0*/#define LPM1 _BIS_SR(LPM1_bits)/*Enter Low Power Mode 1*/#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits)/*Exit Low Power Mode 1*/#define LPM2 _BIS_SR(LPM2_bits)/*Enter Low Power Mode 2*/#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits)/*Exit Low Power Mode

9、 2*/#define LPM3 _BIS_SR(LPM3_bits)/*Enter Low Power Mode 3*/#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits)/*Exit Low Power Mode 3*/#define LPM4 _BIS_SR(LPM4_bits)/*Enter Low Power Mode 4*/#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits)/*Exit Low Power Mode 4*/#endif/*End#defines for C*/*PERIPHERAL FILE MAP*/*SP

10、ECIAL FUNCTION REGISTER ADDRESSES+CONTROL BITS*/#define IE1_ (0 x0000u)/*Interrupt Enable 1*/DEFC(IE1 ,IE1_)#define WDTIE (0 x01)/*Watchdog Interrupt Enable*/#define OFIE (0 x02)/*Osc.Fault Interrupt Enable*/#define NMIIE (0 x10)/*NMI Interrupt Enable*/#define ACCVIE (0 x20)/*Flash Access Violation

11、Interrupt Enable*/#define IFG1_ (0 x0002u)/*Interrupt Flag 1*/DEFC(IFG1 ,IFG1_)#define WDTIFG (0 x01)/*Watchdog Interrupt Flag*/#define OFIFG (0 x02)/*Osc.Fault Interrupt Flag*/#define PORIFG (0 x04)/*Power On Interrupt Flag*/#define RSTIFG (0 x08)/*Reset Interrupt Flag*/#define NMIIFG (0 x10)/*NMI

12、Interrupt Flag*/#define IE2_ (0 x0001u)/*Interrupt Enable 2*/DEFC(IE2 ,IE2_)#define UC0IE IE2#define UCA0RXIE (0 x01)#define UCA0TXIE (0 x02)#define UCB0RXIE (0 x04)#define UCB0TXIE (0 x08)#define IFG2_ (0 x0003u)/*Interrupt Flag 2*/DEFC(IFG2 ,IFG2_)#define UC0IFG IFG2#define UCA0RXIFG (0 x01)#defin

13、e UCA0TXIFG (0 x02)#define UCB0RXIFG (0 x04)#define UCB0TXIFG (0 x08)/*ADC10*/#define _MSP430_HAS_ADC10_ /*Definition to show that Module is available*/#define ADC10DTC0_ (0 x0048u)/*ADC10 Data Transfer Control 0*/DEFC(ADC10DTC0 ,ADC10DTC0_)#define ADC10DTC1_ (0 x0049u)/*ADC10 Data Transfer Control

14、1*/DEFC(ADC10DTC1 ,ADC10DTC1_)#define ADC10AE0_ (0 x004Au)/*ADC10 Analog Enable 0*/DEFC(ADC10AE0 ,ADC10AE0_)#define ADC10CTL0_ (0 x01B0u)/*ADC10 Control 0*/DEFW(ADC10CTL0 ,ADC10CTL0_)#define ADC10CTL1_ (0 x01B2u)/*ADC10 Control 1*/DEFW(ADC10CTL1 ,ADC10CTL1_)#define ADC10MEM_ (0 x01B4u)/*ADC10 Memory

15、*/DEFW(ADC10MEM ,ADC10MEM_)#define ADC10SA_ (0 x01BCu)/*ADC10 Data Transfer Start Address*/DEFW(ADC10SA ,ADC10SA_)/*ADC10CTL0*/#define ADC10SC (0 x001)/*ADC10 Start Conversion*/#define ENC (0 x002)/*ADC10 Enable Conversion*/#define ADC10IFG (0 x004)/*ADC10 Interrupt Flag*/#define ADC10IE (0 x008)/*A

16、DC10 Interrupt Enalbe*/#define ADC10ON (0 x010)/*ADC10 On/Enable*/#define REFON (0 x020)/*ADC10 Reference on*/#define REF2_5V (0 x040)/*ADC10 Ref 0:/1:*/#define MSC (0 x080)/*ADC10 Multiple SampleConversion*/#define REFBURST (0 x100)/*ADC10 Reference Burst Mode*/#define REFOUT (0 x200)/*ADC10 Enalbe

17、 output of Ref.*/#define ADC10SR (0 x400)/*ADC10 Sampling Rate 0:200ksps/1:50ksps*/#define ADC10SHT0 (0 x800)/*ADC10 Sample Hold Select Bit:0*/#define ADC10SHT1 (0 x1000u)/*ADC10 Sample Hold Select Bit:1*/#define SREF0 (0 x2000u)/*ADC10 Reference Select Bit:0*/#define SREF1 (0 x4000u)/*ADC10 Referen

18、ce Select Bit:1*/#define SREF2 (0 x8000u)/*ADC10 Reference Select Bit:2*/#define ADC10SHT_0 (0*0 x800u)/*4 x ADC10CLKs*/#define ADC10SHT_1 (1*0 x800u)/*8 x ADC10CLKs*/#define ADC10SHT_2 (2*0 x800u)/*16 x ADC10CLKs*/#define ADC10SHT_3 (3*0 x800u)/*64 x ADC10CLKs*/#define SREF_0 (0*0 x2000u)/*VR+=AVCC

19、 and VR-=AVSS*/#define SREF_1 (1*0 x2000u)/*VR+=VREF+and VR-=AVSS*/#define SREF_2 (2*0 x2000u)/*VR+=VEREF+and VR-=AVSS*/#define SREF_3 (3*0 x2000u)/*VR+=VEREF+and VR-=AVSS*/#define SREF_4 (4*0 x2000u)/*VR+=AVCC and VR-=VREF-/VEREF-*/#define SREF_5 (5*0 x2000u)/*VR+=VREF+and VR-=VREF-/VEREF-*/#define

20、 SREF_6 (6*0 x2000u)/*VR+=VEREF+and VR-=VREF-/VEREF-*/#define SREF_7 (7*0 x2000u)/*VR+=VEREF+and VR-=VREF-/VEREF-*/*ADC10CTL1*/#define ADC10BUSY (0 x0001u)/*ADC10 BUSY*/#define CONSEQ0 (0 x0002u)/*ADC10 Conversion Sequence Select 0*/#define CONSEQ1 (0 x0004u)/*ADC10 Conversion Sequence Select 1*/#de

21、fine ADC10SSEL0 (0 x0008u)/*ADC10 Clock Source Select Bit:0*/#define ADC10SSEL1 (0 x0010u)/*ADC10 Clock Source Select Bit:1*/#define ADC10DIV0 (0 x0020u)/*ADC10 Clock Divider Select Bit:0*/#define ADC10DIV1 (0 x0040u)/*ADC10 Clock Divider Select Bit:1*/#define ADC10DIV2 (0 x0080u)/*ADC10 Clock Divid

22、er Select Bit:2*/#define ISSH (0 x0100u)/*ADC10 Invert Sample Hold Signal*/#define ADC10DF (0 x0200u)/*ADC10 Data Format 0:binary 1:2s complement*/#define SHS0 (0 x0400u)/*ADC10 Sample/Hold Source Bit:0*/#define SHS1 (0 x0800u)/*ADC10 Sample/Hold Source Bit:1*/#define INCH0 (0 x1000u)/*ADC10 Input C

23、hannel Select Bit:0*/#define INCH1 (0 x2000u)/*ADC10 Input Channel Select Bit:1*/#define INCH2 (0 x4000u)/*ADC10 Input Channel Select Bit:2*/#define INCH3 (0 x8000u)/*ADC10 Input Channel Select Bit:3*/#define CONSEQ_0 (0*2u)/*Single channel single conversion*/#define CONSEQ_1 (1*2u)/*Sequence of cha

24、nnels*/#define CONSEQ_2 (2*2u)/*Repeat single channel*/#define CONSEQ_3 (3*2u)/*Repeat sequence of channels*/#define ADC10SSEL_0 (0*8u)/*ADC10OSC*/#define ADC10SSEL_1 (1*8u)/*ACLK*/#define ADC10SSEL_2 (2*8u)/*MCLK*/#define ADC10SSEL_3 (3*8u)/*SMCLK*/#define ADC10DIV_0 (0*0 x20u)/*ADC10 Clock Divider

25、 Select 0*/#define ADC10DIV_1 (1*0 x20u)/*ADC10 Clock Divider Select 1*/#define ADC10DIV_2 (2*0 x20u)/*ADC10 Clock Divider Select 2*/#define ADC10DIV_3 (3*0 x20u)/*ADC10 Clock Divider Select 3*/#define ADC10DIV_4 (4*0 x20u)/*ADC10 Clock Divider Select 4*/#define ADC10DIV_5 (5*0 x20u)/*ADC10 Clock Di

26、vider Select 5*/#define ADC10DIV_6 (6*0 x20u)/*ADC10 Clock Divider Select 6*/#define ADC10DIV_7 (7*0 x20u)/*ADC10 Clock Divider Select 7*/#define SHS_0 (0*0 x400u)/*ADC10SC*/#define SHS_1 (1*0 x400u)/*TA3 OUT1*/#define SHS_2 (2*0 x400u)/*TA3 OUT0*/#define SHS_3 (3*0 x400u)/*TA3 OUT2*/#define INCH_0

27、(0*0 x1000u)/*Selects Channel 0*/#define INCH_1 (1*0 x1000u)/*Selects Channel 1*/#define INCH_2 (2*0 x1000u)/*Selects Channel 2*/#define INCH_3 (3*0 x1000u)/*Selects Channel 3*/#define INCH_4 (4*0 x1000u)/*Selects Channel 4*/#define INCH_5 (5*0 x1000u)/*Selects Channel 5*/#define INCH_6 (6*0 x1000u)

28、/*Selects Channel 6*/#define INCH_7 (7*0 x1000u)/*Selects Channel 7*/#define INCH_8 (8*0 x1000u)/*Selects Channel 8*/#define INCH_9 (9*0 x1000u)/*Selects Channel 9*/#define INCH_10 (10*0 x1000u)/*Selects Channel 10*/#define INCH_11 (11*0 x1000u)/*Selects Channel 11*/#define INCH_12 (12*0 x1000u)/*Se

29、lects Channel 12*/#define INCH_13 (13*0 x1000u)/*Selects Channel 13*/#define INCH_14 (14*0 x1000u)/*Selects Channel 14*/#define INCH_15 (15*0 x1000u)/*Selects Channel 15*/*ADC10DTC0*/#define ADC10FETCH (0 x001)/*This bit should normally be reset*/#define ADC10B1 (0 x002)/*ADC10 block one*/#define AD

30、C10CT (0 x004)/*ADC10 continuous transfer*/#define ADC10TB (0 x008)/*ADC10 two-block mode*/#define ADC10DISABLE (0 x000)/*ADC10DTC1*/*Basic Clock Module*/#define _MSP430_HAS_BC2_ /*Definition to show that Module is available*/#define DCOCTL_ (0 x0056u)/*DCO Clock Frequency Control*/DEFC(DCOCTL ,DCOC

31、TL_)#define BCSCTL1_ (0 x0057u)/*Basic Clock System Control 1*/DEFC(BCSCTL1 ,BCSCTL1_)#define BCSCTL2_ (0 x0058u)/*Basic Clock System Control 2*/DEFC(BCSCTL2 ,BCSCTL2_)#define BCSCTL3_ (0 x0053u)/*Basic Clock System Control 3*/DEFC(BCSCTL3 ,BCSCTL3_)#define MOD0 (0 x01)/*Modulation Bit 0*/#define MO

32、D1 (0 x02)/*Modulation Bit 1*/#define MOD2 (0 x04)/*Modulation Bit 2*/#define MOD3 (0 x08)/*Modulation Bit 3*/#define MOD4 (0 x10)/*Modulation Bit 4*/#define DCO0 (0 x20)/*DCO Select Bit 0*/#define DCO1 (0 x40)/*DCO Select Bit 1*/#define DCO2 (0 x80)/*DCO Select Bit 2*/#define RSEL0 (0 x01)/*Range S

33、elect Bit 0*/#define RSEL1 (0 x02)/*Range Select Bit 1*/#define RSEL2 (0 x04)/*Range Select Bit 2*/#define RSEL3 (0 x08)/*Range Select Bit 3*/#define DIVA0 (0 x10)/*ACLK Divider 0*/#define DIVA1 (0 x20)/*ACLK Divider 1*/#define XTS (0 x40)/*LFXTCLK 0:Low Freq./1:High Freq.*/#define XT2OFF (0 x80)/*E

34、nable XT2CLK*/#define DIVA_0 (0 x00)/*ACLK Divider 0:/1*/#define DIVA_1 (0 x10)/*ACLK Divider 1:/2*/#define DIVA_2 (0 x20)/*ACLK Divider 2:/4*/#define DIVA_3 (0 x30)/*ACLK Divider 3:/8*/#define DIVS0 (0 x02)/*SMCLK Divider 0*/#define DIVS1 (0 x04)/*SMCLK Divider 1*/#define SELS (0 x08)/*SMCLK Source

35、 Select 0:DCOCLK/1:XT2CLK/LFXTCLK*/#define DIVM0 (0 x10)/*MCLK Divider 0*/#define DIVM1 (0 x20)/*MCLK Divider 1*/#define SELM0 (0 x40)/*MCLK Source Select 0*/#define SELM1 (0 x80)/*MCLK Source Select 1*/#define DIVS_0 (0 x00)/*SMCLK Divider 0:/1*/#define DIVS_1 (0 x02)/*SMCLK Divider 1:/2*/#define D

36、IVS_2 (0 x04)/*SMCLK Divider 2:/4*/#define DIVS_3 (0 x06)/*SMCLK Divider 3:/8*/#define DIVM_0 (0 x00)/*MCLK Divider 0:/1*/#define DIVM_1 (0 x10)/*MCLK Divider 1:/2*/#define DIVM_2 (0 x20)/*MCLK Divider 2:/4*/#define DIVM_3 (0 x30)/*MCLK Divider 3:/8*/#define SELM_0 (0 x00)/*MCLK Source Select 0:DCOC

37、LK*/#define SELM_1 (0 x40)/*MCLK Source Select 1:DCOCLK*/#define SELM_2 (0 x80)/*MCLK Source Select 2:XT2CLK/LFXTCLK*/#define SELM_3 (0 xC0)/*MCLK Source Select 3:LFXTCLK*/#define LFXT1OF (0 x01)/*Low/high Frequency Oscillator Fault Flag*/#define XT2OF (0 x02)/*High frequency oscillator 2 fault flag

38、*/#define XCAP0 (0 x04)/*XIN/XOUT Cap 0*/#define XCAP1 (0 x08)/*XIN/XOUT Cap 1*/#define LFXT1S0 (0 x10)/*Mode 0 for LFXT1(XTS=0)*/#define LFXT1S1 (0 x20)/*Mode 1 for LFXT1(XTS=0)*/#define XT2S0 (0 x40)/*Mode 0 for XT2*/#define XT2S1 (0 x80)/*Mode 1 for XT2*/#define XCAP_0 (0 x00)/*XIN/XOUT Cap:0 pF*

39、/#define XCAP_1 (0 x04)/*XIN/XOUT Cap:6 pF*/#define XCAP_2 (0 x08)/*XIN/XOUT Cap:10 pF*/#define XCAP_3 (0 x0C)/*XIN/XOUT Cap:pF*/#define LFXT1S_0 (0 x00)/*Mode 0 for LFXT1:Normal operation*/#define LFXT1S_1 (0 x10)/*Mode 1 for LFXT1:Reserved*/#define LFXT1S_2 (0 x20)/*Mode 2 for LFXT1:VLO*/#define L

40、FXT1S_3 (0 x30)/*Mode 3 for LFXT1:Digital input signal*/#define XT2S_0 (0 x00)/*Mode 0 for XT2:-1 MHz*/#define XT2S_1 (0 x40)/*Mode 1 for XT2:1-4 MHz*/#define XT2S_2 (0 x80)/*Mode 2 for XT2:2-16 MHz*/#define XT2S_3 (0 xC0)/*Mode 3 for XT2:Digital input signal*/*Comparator A*/#define _MSP430_HAS_CAPL

41、US_ /*Definition to show that Module is available*/#define CACTL1_ (0 x0059u)/*Comparator A Control 1*/DEFC(CACTL1 ,CACTL1_)#define CACTL2_ (0 x005Au)/*Comparator A Control 2*/DEFC(CACTL2 ,CACTL2_)#define CAPD_ (0 x005Bu)/*Comparator A Port Disable*/DEFC(CAPD ,CAPD_)#define CAIFG (0 x01)/*Comp.A Int

42、errupt Flag*/#define CAIE (0 x02)/*Comp.A Interrupt Enable*/#define CAIES (0 x04)/*Comp.A Int.Edge Select:0:rising/1:falling*/#define CAON (0 x08)/*Comp.A enable*/#define CAREF0 (0 x10)/*Comp.A Internal Reference Select 0*/#define CAREF1 (0 x20)/*Comp.A Internal Reference Select 1*/#define CARSEL (0

43、 x40)/*Comp.A Internal Reference Enable*/#define CAEX (0 x80)/*Comp.A Exchange Inputs*/#define CAREF_0 (0 x00)/*Comp.A Int.Ref.Select 0:Off*/#define CAREF_1 (0 x10)/*Comp.A Int.Ref.Select 1:*Vcc*/#define CAREF_2 (0 x20)/*Comp.A Int.Ref.Select 2:*Vcc*/#define CAREF_3 (0 x30)/*Comp.A Int.Ref.Select 3:

44、Vt*/#define CAOUT (0 x01)/*Comp.A Output*/#define CAF (0 x02)/*Comp.A Enable Output Filter*/#define P2CA0 (0 x04)/*Comp.A+Terminal Multiplexer*/#define P2CA1 (0 x08)/*Comp.A-Terminal Multiplexer*/#define P2CA2 (0 x10)/*Comp.A-Terminal Multiplexer*/#define P2CA3 (0 x20)/*Comp.A-Terminal Multiplexer*/

45、#define P2CA4 (0 x40)/*Comp.A+Terminal Multiplexer*/#define CASHORT (0 x80)/*Comp.A Short+and-Terminals*/#define CAPD0 (0 x01)/*Comp.A Disable Input Buffer of Port Register.0*/#define CAPD1 (0 x02)/*Comp.A Disable Input Buffer of Port Register.1*/#define CAPD2 (0 x04)/*Comp.A Disable Input Buffer of

46、 Port Register.2*/#define CAPD3 (0 x08)/*Comp.A Disable Input Buffer of Port Register.3*/#define CAPD4 (0 x10)/*Comp.A Disable Input Buffer of Port Register.4*/#define CAPD5 (0 x20)/*Comp.A Disable Input Buffer of Port Register.5*/#define CAPD6 (0 x40)/*Comp.A Disable Input Buffer of Port Register.6

47、*/#define CAPD7 (0 x80)/*Comp.A Disable Input Buffer of Port Register.7*/*Flash Memory*/#define _MSP430_HAS_FLASH2_ /*Definition to show that Module is available*/#define FCTL1_ (0 x0128u)/*FLASH Control 1*/DEFW(FCTL1 ,FCTL1_)#define FCTL2_ (0 x012Au)/*FLASH Control 2*/DEFW(FCTL2 ,FCTL2_)#define FCT

48、L3_ (0 x012Cu)/*FLASH Control 3*/DEFW(FCTL3 ,FCTL3_)#define FRKEY (0 x9600u)/*Flash key returned by read*/#define FWKEY (0 xA500u)/*Flash key for write*/#define FXKEY (0 x3300u)/*for use with XOR instruction*/#define ERASE (0 x0002u)/*Enable bit for Flash segment erase*/#define MERAS (0 x0004u)/*Ena

49、ble bit for Flash mass erase*/#define WRT (0 x0040u)/*Enable bit for Flash write*/#define BLKWRT (0 x0080u)/*Enable bit for Flash segment write*/#define SEGWRT (0 x0080u)/*old definition*/*Enable bit for Flash segment write*/#define FN0 (0 x0001u)/*Divide Flash clock by 1 to 64 using FN0 to FN5 acco

50、rding to:*/#define FN1 (0 x0002u)/*32*FN5+16*FN4+8*FN3+4*FN2+2*FN1+FN0+1*/#ifndef FN2#define FN2 (0 x0004u)#endif#ifndef FN3#define FN3 (0 x0008u)#endif#ifndef FN4#define FN4 (0 x0010u)#endif#define FN5 (0 x0020u)#define FSSEL0 (0 x0040u)/*Flash clock select 0*/*to distinguish from USART SSELx*/#def