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1、Monte Carlo simulation for better yield and performance-A tutorialstart System requirementStatistical analysis include process,mismatch effectsInitial designDesign meets the goal?endNOYESMonte Carlo simulation for better yield and performance Some design may degrade in performanceOverall design yiel
2、d could be unexpectedly low If fabrication process parameter and device mismatch effect on same die are not taken in to account thenHence statistical analysis must find a high place in design cycleWe will perform Monte Carlo analysis on an RF-front end LNA and compare the result if no statistical an
3、alysis is done.We will also see how to analyze yield and scalar data in Monte Carlo with the help of Low pass filter example.Monte Carlo simulationMonte Carlo simulation(example)LinearityInput matchingBias N/WOutput matchingCascode arch.to reduce feedback capacitanceRF-front end(LNA)Knowing System r
4、equirement Initial design based on requirement like noise,gain,narrow or wide band.Monte Carlo simulationCadence simulation setup(Normal)1.Choosing affirma analog artist2.Choosing Spectre simulatorChoosing model file,which contains all MOS,reg.,cap model parameters.Monte Carlo simulation1.Choose set
5、up model libraries2.Browse and choose model file in the directoryCadence simulation setup(Normal)Set up analysis(dc,ac,sp etc.),create netlist and run simulatorMonte Carlo simulation1.Choose analysis to run2.Choose output to plot3.Create netlist and runCadence simulation setup(Normal)Plotting result
6、sMonte Carlo simulation1.Choose direct plot for analysis2.Click to view the desired result3.Analyze waveformCadence simulation setup(Normal)Monte Carlo modeling in Cadence spectre simulator Process Section-describes manufacturing parameter,their statistical variation and a model for device that calc
7、ulates its(width,length,cap,res.Etc.)according to process parameter.Design-Specific Section designer according to his need can specify Monte Carlo analysis.For example in a current mirror circuit,matched transistors are used and designer can give some correlation factor between these matched transis
8、tor.Monte Carlo simulationCadence simulation setup(Monte Carlo)Typical Model FileProcess Section1.All parameter sets to their nominal value,no statistical variation defined2.Model(NMOSs Rg)is calculated using nominal parameter value21Monte Carlo simulationCadence simulation setup(Monte Carlo)Definin
9、g process,mismatch parameter as statistically assigned valueAssesses the device mismatch on different die,which could have gone through some different process parameters during fabrication.Assesses the device mismatch on same die,which could have gone through some different process parameter.Variati
10、on defined as a distributed functionMonte Carlo simulationProcess SectionCadence simulation setup(Monte Carlo)Design Specific SectionThis includes the circuit connectivity(two resistors,and corresponding current sources that feed them)Defining correlation between two devices(R1,R2)Note:Alternatively
11、 this information can also be inserted through Artist Monte Carlo Tool.Monte Carlo simulationCadence simulation setup(Monte Carlo)Monte Carlo simulationModel file used for LNA exampleNoteThis is not based on foundry data but modeled for illustrative purposes.Cadence simulation setup(Monte Carlo)Mont
12、e Carlo simulation After Initial design that meets the system requirement,statistical analysis must have to be carried out.1.Make sure the addition of process and mismatch parameter section in model file.2.Make certain to include the particular section(for exa.Stats in spectre)in simulation model li
13、brary3.Go to toolMonte Carlo in affirma analog artistCadence simulation setup(Monte Carlo)Monte Carlo simulationChoose no of iteration(default=100)1.Choose which variation to include Processdevice mismatch effect on two diff.die Mismatchdevice mismatch effect on same die 2.Click if you want to see t
14、he family of curve i.e.curve from each iteration3.Define the expressions/signals on which Monte Carlo analysis will be performed.Note:calculator can also be used to get these expressionFinally run the analysisCadence simulation setup(Monte Carlo)Monte Carlo simulation(Analyzing waveform)MatchingNorm
15、al simulation(without statistical variation)Monte Carlo Simulation(with statistical variation)Process parameter and mismatch effect Input&Output matching N/WDEGRADESOverall design performance(noise,gain etc.)DEGRADESS11S22Monte Carlo simulation(Analyzing waveform)Matching(VSWR):It tells how well inp
16、ut and output N/W are matched.Monte Carlo simulationNormal simulationVSWR1VSWR2Variations in VSWRMonte Carlo simulation(Analyzing waveform)Matching(forward and reverse transmission gain)It has deteriorated the performance significantly,as a minimum S12 and maximum S21 value is desirable.Normal simul
17、ationMonte Carlo simulationS12S21Monte Carlo simulation(Analyzing waveform)Normal simulationMonte Carlo simulationStability:A Kf value 1,is desired for an stable amplifierKf value has become 1,and consequently creating a potential unstability,hence a large margin is required at initial design phase.
18、Stability factorMonte Carlo simulation(Analyzing waveform)Normal simulationMonte Carlo simulationNoise PerformanceAs visible,design has a robust noise performance at desired band(2.4-2.5 GHz)BUT.Noise figurePeriodic Output noiseMonte Carlo simulation(Analyzing waveform)But LNA as an RF-front end has
19、 to provide enough gain with maximum noise suppression to maintain an allowable SNR at demodulators input.It fails to meet the gain requirementGainMonte Carlo simulationWe will quickly go over another example of low pass filter and see how to analyze scalar data and yield through Monte Carlo simulat
20、ionMonte Carlo simulationInitial Design:Circuit designing according to system requirementLow-Pass FilterMonte Carlo simulation1.Running normal analysis2.Specifying statistical variation in model file3.Running Monte Carlo analysis123Cadence simulation setup(Monte Carlo)Monte Carlo simulationSimulatio
21、n shows db20 and phase values are greatly affected by statistical variations introduced in transistor.Hence the need for redesigning the circuit(Analyzing results)Monte Carlo simulation(Analyzing Scalar data)1.Choose resultsplot Histogram2.Choose parameters to plot3.Analyze the histogram appeared in
22、 waveform windowMonte Carlo simulation1.Choose results specification limits2.Set bounds and limits3.Choose Results yield simple in analysis window4.Set suppression value for yield5.Analyze yieldOnly 64%iterations passes the specified limits for bandwidth and ymax (Analyzing Yield)Monte Carlo simulat
23、ion (PLL Components)OverviewReference clockDetector outputLoop filter responseOscillator outputClock divider output Phase/frequency detector determines the difference between the phase or frequency of two signals The loop filter removes the high-frequencies from the voltage-controlled oscillator(VCO
24、)controlling voltage The VCO produces and output frequency controlled by a voltageMonte Carlo simulation (PLL Components)Noise SourcesDetector noiseVCO noise-Quantization noiseIn PLL design it is highly desirable to be able to see the impact of all noise sources,which in turn affects the overall PLL
25、 performance.Due to reference jitter Due to variation in control voltageDue to uncertainty involved in discretizationMonte Carlo simulation (VCO)An oscillator is a circuit capable of maintaining electric oscillations.Frequency of oscillation=1/(LC)1/2Controlled by voltage dependent capacitance(varac
26、tor)Power efficient since bias current is shared between the two transconductors.Complimentary Cross-Coupled LC VCOequivalentFor operation in current-limited regime:VO =(4/).Ibias.Req(Ideal switching)VO(apx)=Ibias.Req (High frequency)Causes of spectral purity degradation(phase noise):1.)Random noise
27、 in the reference input,the PFD,loop filter and VCO(also dividers if the PLL is a frequency synthesizer)2.)Spurious sidebands high energy sidebands with no harmonic relationship to the generated output signal.It is systematic in origin.Why is spectral purity important?Monte Carlo simulation (VCO Pha
28、se Noise)Phase noise produces adjacentchannel interferencePhase noise can degrade thesensitivity of a receiver due toreciprocal mixingMonte Carlo simulation (VCO Phase Noise)How do the process and mismatch variation affect phase noise?-we will perform monte carlo analysis to assess this.Step1 Varyin
29、g the process parameter only Step2 investigating the device mismatch(in diff VCO one side mismatched to the other)in presence of process variationThe statistics block contains the distributions for parameters:Distributions specified in the process block are sampled once per Monte Carlo run,are appli
30、ed at global scope,and are used typically to represent batch-to-batch(process)variations.Distributions specified in the mismatch block are applied on a per-subcircuit instance basis,are sampled once per subcircuit instance,and are used typically to represent device-to-device(on chip)mismatch for dev
31、ices on the same chip.Cadence Spectre modeling:Monte Carlo simulation (VCO Phase Noise)model fileDefine statistical blocks in the model file(ideally it should be provided from the foundry)Process sectionMismatch sectionMonte Carlo simulation (VCO Phase Noise)STEP-1Running Monte Carlo for process var
32、iation onlyNormal simulationMonte Carlo simulationWith applied statistical variation(in model file)an increase in noise can be observed,and at this run resulted noise is worst and unacceptable.Monte Carlo simulation (VCO Phase Noise)STEP-2Running Monte Carlo for mismatch in 2 sides of Diff.VCONormal
33、 simulationMonte Carlo simulationAgain similar looking but not the same results appears and noise at this run is unacceptable.Note:When the same parameter is subject to both process and mismatch variations,the sampled process value becomes the mean for the mismatch random number generator for that p
34、articular parameter.Monte Carlo simulation (VCO Phase Noise)-more insight To get more insight we will vary only few parameter and check how values are assigned for different run as well as the simulation result Defining variation for only two parameters in the model file-Vth-tox Monte Carlo simulati
35、on (VCO Phase Noise)-more insight Here both nmos(pmos)transistors have been assigned same process variation.In each run they take on different parameter according to distribution definedProcess variation onlyNM0NM1PM1PM0Monte Carlo simulation (VCO Phase Noise)-more insight Process and Mismatch both
36、variation together,with correlation of 0.2 between the two nmos(pmos)transistorAs conspicuous each nmos(pmos)transistor is getting different parameter value in each run.Monte Carlo simulation (VCO Phase Noise)-more insight Process variation onlyProcess&mismatch variation As visible in the case of pr
37、ocess variation with device mismatch noise has been increased.Monte Carlo simulation (PLL at a glance)In a PLL all these process variation can degrade its overall performance significantly.To see the impact of process variation we probe the output after the loop filter.Monte Carlo simulationAs clear
38、 in one case control voltage(i.e.loop filter output)is ramping rapidly compare to other and thus will result in different performance.Monte Carlo simulationIn our design PLL has a settling time of 65 us.To simply run the analysis(transistor level)for this much period may take 2-3 days on a single ma
39、chine.To do monte carlo simulation even for 10 run will make the situation worse.To speed up Monte Carlo analysesto make them run in minutes as opposed to days-We need to reduce the run time and can utilize Parallel simulation.-Such as variance reduction technique can be employed.Monte Carlo simulat
40、ion(Seed no¶llel simulation)Note:(1)Input file should have.scs extension(for exa.input.scs)(2)In spectre one can not specify different seed from GUI(by default it always takes seed=1).If Monte Carlo simulation for different seed is required then.Step 1.Create netlist(input file)a)Either from ana
41、log artist or b)Tools monte carlo simulationcreate_input_filesSeedMonte Carlo simulationMonte Carlo simulation(Seed no¶llel simulation)Step 2.Edit input.scs file manuallyedit SEED=?line(number you want)SeedMonte Carlo simulationMonte Carlo simulation(Seed no¶llel simulation)Step 3.Run spectr
42、e from command line with option for example.spectre -env artist4.4.6+log./psf/spectre.out-format psfbin-raw./psf input.scsHere one should execute spectre command(or executable file)from the netlist directory.For example one wants to simulate“PLL”design from command lineThen go to your simulation dir
43、ectory cd/simulation/pll/spectre/schematic/netlist and here execute spectre commandSeedMonte Carlo simulationMonte Carlo simulation(Seed no¶llel simulation)Step 4.Results can be plotted with either from calculator or from Monte Carlo tool.Seed=1Seed=11Seed=3Fig:Plots for different seed value sim
44、ulationSeedMonte Carlo simulation(Seed no¶llel simulation)Another way of doing similar thing(giving different seed value)from GUI would be to start simulation from different run,or say to skip some initial run as shown in the fig.But beware skipping these runs could take much longer time for a c
45、omplex designHere it will skip first 10 runs and simulate from 11th to 110th run for 100 iterationThis is quite similar to assigning different seed value.A way around from GUIMonte Carlo simulation(Seed no¶llel simulation)Running multiple analysis from one file This can be done by defining multi
46、ple monte carlo analysis statement in the input file as shown below Note:For each analysis a different name to child analysis(for example ac,dc,tran)and to output file has to be assigned.Analysis 1Analysis 2Monte Carlo simulation(Seed no¶llel simulation)Running script for executing multiple file
47、s(sequentially)This can be done by making an executable file as shown and running it from command windowNOTE:In all cases spectre command(or executable file)must be excited from the netlist directory.These file can be used to simulate different design as well as same design(with different seed value
48、 in it)Parallel Simulation Monte Carlo simulation(Seed no¶llel simulation)One can easily set up queues,where a particular queue is set up using the built in CadenceLBS system.1.Create a configuration file:queueName numberOfMachines machine1 numberOfJobs machine2 numberOfJobs queue2 numberOfMachi
49、nes.e.g.parallelQueue 1 linuxMachine 4 2.Pick a machine as your queue manager,and then run:cdsqmgr/path/to/the/queue_config 3.Before running DFII,do:setenv LBS_CLUSTER_MASTER queueMachineName where queueMachineName was the machine you ran cdsqmgr on.4.Then one can submit Artist jobs as distributed a
50、s shown in the.next slideParallel Simulation Monte Carlo simulation(Seed no¶llel simulation)Setting for distributive processing1.from analog artist go to 2.set distributive and assign jobs to all machine Monte Carlo simulation(Seed no¶llel simulation)References:1.Lecture notes of Michael Per