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1、IBMPCAT硬件架构与硬件架构与动作原理动作原理IBM PC/AT 原版電路之功能方塊的內容原版電路之功能方塊的內容1.系統時脈電路系統時脈電路2.DRAM解碼電路解碼電路3.RAS&CAS產生電路產生電路4.DRAM偵測電路偵測電路5.DRAM定址電路定址電路6.ROM Access電路電路7.Decoder8.等待電路等待電路9.刷新要求電路刷新要求電路10.DMA 控制電路控制電路11.系統中斷電路系統中斷電路12.系統計時系統計時/計數器電路計數器電路13.鍵盤控制器電路鍵盤控制器電路14.及時時脈電路及時時脈電路15.NMI控制電路控制電路16.Shut-down LogicFig
2、ure:Decoder(PC/AT original schematic)HLDA-DMA1CS-INTR1CS-T/C CS-PPI CS-PG REG CS-INTR2 CS-DMA2 CS-CS28700 1FH203FH405FH607FH809FHA0BFHC0DFHE0FFHXA5XA6XA7XA9XA8-ACK-ACK+ACK-MASTERY77Y69Y510Y411Y312Y213Y114Y015G2A4G2B5G16A1B2C3U123ALS138IBM PC/AT IO Port Addresses1.Range 00HFFH:System board2.Range 100
3、3FFH:I/O Channel3.00H1FH:DMA Controller 1 Registers4.20H3FH:Interrupt Controller 1 Register5.40H5FH:Programmable Interrupt Timer6.60H64H:keyboard Controller buffer7.70H:CMOS RAM address register port8.71H:CMOS RAM data register Port9.80H:Manufacturing Test Port10.81H8FH:DMA page table address reg.11
4、.A0HBFH:Programmable interrupt ctrl 212.C0HDFH:DMA Controller 2 Register13.F0HFFH:Math Coprocessor regs.14.170H177H:Fixed disk 1 registers15.1F0H1F7H:Fixed disk 0 registers16.200H20FH:Game control port17.201H:Game Port I/O Data18.278H27AH:Parallel Port 3 registers19.2F8H2FFH:Serial Port 2 registers2
5、0.370H377H:Diskette Controller 1 reg21.378H37AH:Parallel Port 2 registers22.3BCH3BEH:Parallel Port 1 registers23.3F0H3FFH:Diskette Controller 0 reg24.3F8H3FFH:Serial Port 1 registers25.3C0H3CFH:VGA I/O Port registers8042 Control Register(I/O Port Address:61H)1.Read/Write status2.Bit 7=1 Parity check
6、3.Bit 6=1 Channel check4.Bit 5=1 Timer 2 output5.Bit 4=1 Toggle with each refresh request6.Bit 3=1 Channel check enabled7.Bit 2=1 Parity check enabled8.Bit 1=1 Speak data enabled9.Bit 0=1 Timer 2 gate to speaker enabled10.System buffer 36 pin slotSD8SD15 62 pin slotSD0SD7U74 80286U8382288U7680287U66
7、ALS245U67LS646U5ALS245U102ALS245U11ALS24574LS612MC146818804282548237*28259*2U113ALS245RAMROMA0 A23D8D15D0D7SD0 0 SD7主機板內主機板內DATA Bus的流程的流程External BufferSD8SD15SD0SD7MD8MD15MD0MD7D8D15D0D7SD0 0 SD7IVL ByteBufferSD8SD15XD0 XD7MemoryBufferSD0SD7DIRDIR245GGATE24574ALS245ABU113SD0-SD7SD8-SD15ALS04U97F10
8、U97F10U97F10ALS04DENNPCS#XBHE#CNRL OFF#XA0DT/R#LSA0DT/R#CKBSRBDIRCKASRAABU67E1274LS646GDIRBDT/R#74ALS245U66AD8-D15D0-D7高/低位元組和系統緩衝器簡圖INTAXIORXIOWI/O DIR功能描述 X 0 1000H 0F7HB ACPU對主機板I/O埠設備讀取 X 0 10F8H 0FFHA BCPU對80287埠設備讀取 X 0 1100H 3FFHA BCPU對擴充板I/O埠設備讀取 X 1 0000H 0F7HA BCPU對主機板I/O埠設備寫入 X 1 00F8H 0F
9、FHA BCPU對80287埠設備寫入 X 1 0100H 3FFHA BCPU對擴充板I/O埠設備寫入 X 1 X XA BCPU不在I/O的動作 0 X X XB A8259 送中斷向量給CPU外在緩衝器控制線路外在緩衝器External Buffer的OIR控制得分析SA0SA19刷新位址产生器74LS590U7228 S 42SA0SA1962 脚 位 扩 充 值 A0 A1 A1980286 A20 A2374LS6128237*2ROM其它与XBUS有关的组件CONVA0A0A17 ALS 244A19 U7574ALS573*3U56U60U73G OEA17A23A1A19SA
10、0SA7SA074ALS245*2U48DIR U38SA1SA16ALS245U65DIRLA17LA23LA17LA2336脚 位 扩 充 值A17A23A17A19XA1XA16ALE CPU HLDAMASTER74F158*3SA0SA18RAMMA0MA9 ADDR SELDMAAENHOLDMASTER位址汇流排方块图位址汇流排方块图HLDA65U7480286ALE5U8382288RESET12U8282284111213U11ALS08456U80ALS32Y5Y7Y3Y9A1510A13A17A11G19U75ALS244CPU HLDAHLDA-MASTERALE+AC
11、KGATE ALE+RESETHLDAAENBALERESET DRVAEN,BALE,RESET DRV:AT Slot signals.AEN,BALE,RESET DRV 信號的流程信號的流程From AT slotHLDAS14S05M/IO67U7480286S13S019M/IO18MRDC8MWDC9IORC11IOWC13U8382288A12A28A34A42G1Y118Y212ALS244D3D4D6D8D9D7D5D2G11OE1Q12Q13Q14Q15Q16Q17Q18Q19ALS 573ALS573-CS ROMF16GATE ALE“LOW”-MEG CS-LMEG
12、 CS82S147A23A22A21A20A19A18A17+REFRESH-RAM SELS0S1M/IO#-MEMR-MEMW-LMEGCSU49-MEMR-MEMW-SMEMR-SMEMW-IOR-IOWD06D17D28D39D411D512D613D714A617A716A01A12A23A34A45A518A619G15U?Memory Read/Write 於 IO Read/Write 控制信號在CPU於AT slot之間的流程-LMEG CS:Dccoder Memory 在1MB以內記憶體空間MRDC#8MWTC#9IOWC#11IORC#12U8382288B15B16B
13、17B11B12B18A2A4A8A9A3A5DIR1G#U89LS245IOW#1IOW#2MEMW#3MEMR#4U1118237 *2CLR1PR4D2CLK3Q5U77F74123U77LS1251234567891011121314151617181920U87PAL16L8U122-MEMR-MEMW-IOR-IOW-IOW-IOR-MEMW-MEMRAT SLOTSA0SBHE-DMA AENLOWPULL UP-XMEMR-DMA MEMRDMA CLK-RESET-XMEMR-DMA MEMR-XMEMW-XIOR-XIOWXA0XBHE+5XBHEXA0+RAS-MEMW-
14、IOR+AIOWQ1-IO CS16-AEN 1-AEN 2Q4+FSYS16-RES/OWSDATA CONVDIR 245GATE 245-DMA AEN-END CYCMemory Read/Write 与与IO Read/Write 控制信號在控制信號在82288与与8237之之 間的流程間的流程KT9 System Block DiagramNS87570MS1535+DC to DC Buck Converter Logic&Delay circuit -DNBSWON-NBSWON-SUSB-SUSCSUSONMAINONVRONHWPG_POWERNPWROKNB_PWROKS
15、B_PWROKCPU_PWRGD(1)RVCC(2)(3)(4)(5)(6)(7)PWR BUTTONKT9 Power On Block DiagramSystem Start Steps(1)1.Power ON/OFF Button PC87570(PCU)2.PC87570 M1535+(South Bridge)3.M1535+PC87570 SUS Power(3VSUS、5VSUS)4.PC87570 Main Power(3V、5V、2.5V)VHcore-NBSWON-SUSB/-SUSC-DNBSWONSUSONMAINON-VRON1.When we push the P
16、ower Button,the signal -NBSWON will be generated and send to the PCU(PC87570).2.As the PCU receives the-NBSWON,it will send the-DNBSWON to the south bridge(M1535+).3.Then the SB asserts -SUSB and-SUSC signals to the PCU.4.The PCU will send the SUSON,MAINON and VRON for suspend power,main power and V
17、Hcore generating.System Start Steps(1)4.1 PC87570SUSONSC1470PQ51/PQ16PQ3/PQ55 2.5VSUS12VSPQ8PQ403VSUS5VSUS4.2 PC87570MAINONPQ61PQ44PQ50/PQ39LP2996PQ7/PQ573VAGP 2.5V12V VTT_DDRPQ8PQ403V5VSUSDMAIND4.3 PC87570-VRON 2.5VSUSHIP6301VHcoreSystem Start Steps(2)HWPG5.MAX1632HWPG-POWERPC875706.PC87570NPWROKNB
18、_PWROKRS200MP(NB)NB_PWROKU66PWROK 7.SB_PWROKM1535+Q58Q59CPU_PWRGDPWRGOODCPUSystem Start Steps(3)-SYS_RST8.M1535+-PCI_RST-PCI_RST9.-NB_PCIRSTRS200MPSB_PWROK-PCIRSTI/O Devices10.RS200MP-CPU_RSTCPU*CPU and all I/O devices have been reset.System Start Steps(4)11.CPU Memory Code Read North Bridge -Addres
19、s(A31#A3#):FFFF FFF012.North Bridge:CPU Command PCI Command CPU Address PCI Address13.North Bridge Memory Read South Bridge -Address(AD31 AD0):FFFF FFF014.South Bridge:PCI Command ISA Command PCI Address ISA AddressSystem Start Steps(4)11.CPU will generate the first command-Memory Code Read to the N
20、orth Bridge,and the Host address-(A31#A3#):FFFF FFF0.12.When the NB receives the CPU command and Host address,It will translate the CPU command to PCI command-(Memory Read),and translate the Host Address to the PCI address-(AD31#AD0#):FFFF FFF0.13.Then the NB sends the PCI command and PCI address to
21、 the South Bridge via the PCI Bus.14.AS the SB receives the PCI command and PCI address,it will translate the PCI command to the ISA command-(MEMR#)and the PCI address to the ISA address-(A19A0):FFFFF.System Start Steps(5)15.South Bridge MEMR#System ROM -Address(SA17 SA0):1FFF016.ROM Data ISA Data B
22、us South Bridge17.South Bridge PCI Data Bus North Bridge18.North Bridge Host Data Bus CPU19.CPU:Decode and Execute (Go To Step 11:Decode&Execute)System Start Steps(5)15.THE SB will drive the MEMR#command to the System ROM and access the ROM address(SA17 SA0):1FFF016.So the ROM Data will be transferr
23、ed to South Bridge through the ISA Bus17.And then through the PCI Bus,the South Bridge will send the PCI date to the North Bridge 18.At the last the North Bridge will send Host data to the CPU through the Host Bus.19.After the CPU fetch the host data which is transferred from North Bridge,it begins
24、to Decode&Execute(Go To Step 11:Decode&Execute).The first Execution Instruction in PC AT1.CPU Address:A31 A3=FFFF FFF02.CPU:CS:IP=F000:FFF0 FFFF03.ISA Address:SA17 SA0 =1FFF04.ISA Data:1FFF0:EA 5B E0 00 F0 30 37 2F5.1FFF8:31 35 2F 39 39 00 FC 006.5.EA 5B E0 00 F0=Long Jump F000:E05B7.30 37 2F 31 35
25、2F 39 39=07/15/99POST(Power-On Self Test)Process POST tests and initializes the following:1.The central processing unit(CPU)2.The ROM BIOS(checksum)3.The CMOS RAM4.The Intel 8237 DMA Controller5.The keyboard controller6.The base 64K System RAM7.The Programmable Interrupt controller8.The Programmable
26、 Interrupt Timer9.The cache controller10.COMS RAM configuration data11.The CRT controller12.RAM memory above 64K13.The keyboard14.Diskette drive A availability15.The serial interface circuitry16.The diskette controller 17.The fixed disk controller 18.Any additional hardware AWARD BIOS POST Test code
27、 listingPOST POST CODECODEAward POST Routine DescriptionC0Turn off chipset cache.01Test processor flag register.02Test all processor registers except SS,SP and BP with pattern FF and 00.03Initialize Chips(RTC,8254,8237,8259),Reset math coprocessor,Clear CMOS shutdown byte and page register.04Test DR
28、AM refresh05Blank video,keyboard controller initialization.07Test CMOS interface and battery status.BEInitialize chipset with power on BIOS defaults.C1Memory-presence test.(OEM Specific-Test to size on-board memory)C5C6Early Shadow.(OEM Specific-Early Shadow enable for fast boot)Cache presence test.
29、(External cache size detection)08Setup low memory(base 64K memory test).09Early cache initialization(Cyrix CPU initialization,Cache Initialization.)0ASetup interrupt vector table.0BTest CMOS RAM checksum,load default value if test is bad.0CInitialize keyboard(detect keyboard type and set NUM_LOCK st
30、atus)0DInitialize and detect video adapter interface.0ETest video memory,write sign-on message to screen.Setup shadow RAM-Enable shadow according to setup.0FTest DMA controller 0.10Test DMA controller 1.11Test DMA page registers(74612)14Test Timer 0 counter 215Test 8259-1 interrupt mask register(por
31、t 21H)16Test 8259-2 interrupt mask register(port A1H)17Test stuck 8259s interrupt bits 18Test 8259 interrupt functionalityIBM PC/AT System RAM Data Area(1).Range:00H to 3FFH1.Interrupt Vector Table 2.Interrupt Vector Stored as3.offset/segment format4.(2).Range:400H to 4FFH5.BIOS Data Area6.Data defi
32、nitions related to BIOS fixed7.disk,diskette,Keyboard,video,The first two words of expansion ROM areaVGA BIOS(CS:IP=C000:0000)ROM Byte Value 0 55H 1 AAH 2 ROM Length in 512-byte blocks 3 Entry point for ROM initialization (via FAR CALL)Differences(vs.CPU/PCI/ISA)CPU PCI ISA1.Speed 66/100/133 33/66 8
33、 MHz2.Power Vcore&Vio 3.3V 5V3.Address Bus 32/(36)32/64 24 bit 4.Data Bus 64 32/64 16 bit5.Address/Data Separate Shared Separate6.Control Bus(Commands/Control signals)CPU PCI ISA6.1 Types 8/(32)16 46.2 Start ADS-FRAME-BALE6.3 End Ready-IRDY-&TRDY-IOCHRDY7.ID VPID0:3 IDSEL-(Decoder)BUS CYCLE DEFINITI
34、ONM/IO#D/C#W/R#Bus Cycle Initiated 0 0 0 Interrupt Acknowledge 0 0 1 Halt/Special Cycle 0 1 0 I/O Read 0 1 1 I/O Write 1 0 0 Code Read 1 0 1 Reserved 1 1 0 Memory Read 1 1 1 Memory Write Transaction REQ4:0#(First Clock)REQ4:0#(Second Clock)4321043210Deferred Reply00000 Rsvd(ignore)0 0001 Interrupt A
35、cknowledge 01000DSZ#00Special Transactions01000DSZ#01Rsvd(Central agent response)01001DSZ#1Branch Trace Message01001DSZ#00Rsvd(Central agent response)01001DSZ#01I/O Read10000DSZ#LEN#I/O Write10001DSZ#LEN#Rsvd(Ignore)1100DSZ#Memory Read&InvalidateASZ#010DSZ#LEN#Rsvd (Memory Write)ASZ#011DSZ#LEN#Memor
36、y Code ReadASZ#1D/C#=00DSZ#LEN#Memory Data ReadASZ#1D/C#=10DSZ#LEN#Memory Write(may not be retried)ASZ#1W/WB#=01DSZ#LEN#Memory Write(may be retried)ASZ#1W/WB#=01DSZ#LEN#Transaction Type Defined by REQ#SignalsTable LEN1:0#Signal Data Transfer LengthsLEN1:0#Request Initiators Data Transfer Length 00 0
37、-8 Bytes 01 16 Bytes 10 32 Bytes 11 Reserved ASZ1:0#Description 0 0 0=A35:3#4GB 0 14GB=A35:3#64GB 1 x Reserved Table ASZ1:0#Signal Decode POWERGOOD Relationship at Power-OnVCCcoreVCCL2PWRGOODRESET#Clock1 msRatioBCLKRatio of processor Core Ratio of processor Core Frequency Frequency to toSystem Bus F
38、requencySystem Bus Frequency LINTLINT11LINTLINT00IGNNEIGNNE#A20M#A20M#ReservedHLHH3/2HHLH2HHHH5/2LHLL3LLHL7/2LHHL4LLLH9/2LHLH5LLHH11/2LHHH6HLLL13/2HHLL7HLHL15/2HHHL8HLLHSystem Bus To Core Frequency Multiplier ConfigurationProcessorPCI Local BusBridge/MemoryControllerCacheDRAMLANSCSIExp BusXfaceBase
39、I/OsISA/EISA Micro ChannelAudioMotion videoGraphicsADDRESS PHASEDATA PHASEDATA PHASEDATA PHASEBUS TRANSACTIONFigure:Basic Read Operation123456789CLKFRAME#ADADDRESSDATA-1DATA-2DATA-3C/BE#BUS CMDBE#SIRDY#WAITDATA TRANSFERWAITDATA TRANSFERWAITDATA TRANSFERTRDY#DEVSEL#Command DefinitionC/BE3:0#Command T
40、ype 0000 Interrupt Acknowledge0001 Special Cycle0010 I/O Read0011 I/O Write0100 Reserved0101 Reserved0110 Memory Read0111 Memory Write 1000 Reserved1001 Reserved1010 Configuration Read1011 Configuration Write1100 Memory Read Multiple 1101 Dual Address Cycle 1110 Memory Read Line 1111 Memory Write an
41、d InvalidateDATA PHASEDATA PHASEDATA PHASE BUS TRANSACTION123456789CLKFRAME#ADADDRESSDATA-1DATA-3C/BE#BUS CMDBE#S-3IRDY#WAITDATA TRANSFERWAITDATA TRANSFERWAITDATA TRANSFERTRDY#DEVSEL#DATA-2BE#S-1BE#S-2ADDRESS PHASEFigure:Basic Write OperationPCICOMPLIANTDEVICEAD63:32C/BE7:4#AD31:00C/BE3:0#PARAddress
42、&DataInterface ControlFRAME#IRDY#TRDY#STOP#CLKSERR#IDSELPERP#GNT#REQ#STOP#RST#Arbtration(masters only)Error ReportingSystemTDITDOTCKTMSTRST#64-BitExtensionInterface ControlInterruptsJTAG(IEEE 1149.1)INTA#INTB#INTC#INTD#PAR64REQ64#LOCK#ACK64#Figure:PCI Pin ListRequired PinsOptional PinsCompact PCI fe
43、ature(part 1)1.33 and 66 MHz PCI performance2.32-and 64-bit data transfers3.8 CompactPCI slots per bus segment at 33 MHz4.5 CompactPCI slots per bus segment at 66 MHz5.Industry standard software support6.3U small form factor(100 mm by 160 mm)7.6U form factor(233.35 mm by 160 mm)Compact PCI Features(part 2)8.IEEE(1101.1,1101.10 and 1101.11)Eurocard packaging9.Wide variety of available I/O10.System Management Bus (CompactPCI Specification PICMG 2.0 D3.0 September 24,1999)