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1、现代CMOS工艺基本流程Silicon Substrate P+Silicon Epi Layer P Pad Oxide热氧化热氧化形成一个SiO2薄层，厚度约20nm高温，H2O或O2气氛缓解后续步骤形成的Si3N4对Si衬底造成的应力2Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideSi3N4淀积Si3N4淀积厚度约250nm化学气相淀积(CVD)作为后续CMP的停止层3Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresist光刻胶成形光刻胶成形厚度约
2、0.51.0um光刻胶涂敷、曝光和显影用于隔离浅槽的定义4Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresistSi3N4和SiO2刻蚀Si3N4和SiO2刻蚀基于氟的反应离子刻蚀(RIE)5Silicon Substrate P+Silicon Epi Layer P-Silicon NitridePhotoresistTransistor Active AreasIsolation Trenches隔离浅槽刻蚀隔离浅槽刻蚀基于氟的反应离子刻蚀(RIE)定义晶体管有源区6Silicon Substrate P+Si
3、licon Epi Layer P-Silicon NitrideTransistor Active AreasIsolation Trenches除去光刻胶除去光刻胶氧等离子体去胶，把光刻胶成分氧化为气体7Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS TransistorSilicon DioxideFuture NMOS TransistorNo current can flow through here!SiO2淀积SiO2淀积用氧化物填充隔离浅槽厚度约为0.51.0um，和浅槽深度和几何形状有关化学
4、气相淀积(CVD)8Silicon Substrate P+Silicon Epi Layer P-Silicon NitrideFuture PMOS TransistorFuture NMOS TransistorNo current can flow through here!化学机械抛光化学机械抛光(CMP)CMP除去表面的氧化层到Si3N4层为止9Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS Transistor除去Si3N4除去Si3N4热磷酸(H3PO4)湿法刻蚀，约18010T
5、rench OxideCross SectionBare Silicon平面视图完成浅槽隔离(STI)11Silicon Substrate P+Silicon Epi Layer P-Future PMOS TransistorFuture NMOS TransistorPhotoresist光刻胶成形光刻胶成形厚度比较厚，用于阻挡离子注入用于N-阱的定义12Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorPhotoresistN-WellPhosphorous(-)Ions磷离子注入磷离子注入高能磷离子注入形成局部
6、N型区域，用于制造PMOS管13Silicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN-Well除去光刻胶14PhotoresistSilicon Substrate P+Silicon Epi Layer P-Future NMOS TransistorN-Well光刻胶成形光刻胶成形厚度比较厚，用于阻挡离子注入用于P-阱的定义15Silicon Substrate P+Silicon Epi Layer P-PhotoresistN-WellBoron(+)IonsP-Well硼离子注入高能硼离子注入形成局部P型区域，
7、用于制造NMOS管硼离子注入16Silicon Substrate P+Silicon Epi Layer P-N-WellP-Well除去光刻胶17Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well退火退火在6001000的H2环境中加热修复离子注入造成的Si表面晶体损伤注入杂质的电激活同时会造成杂质的进一步扩散快速加热工艺(RTP)可以减少杂质的扩散18Trench OxideN-WellP-WellCross Section完成N-阱和P-阱平面视图19Silicon Substrate P+Silicon Epi Layer P-P
8、-WellN-Well Sacrificial Oxide牺牲氧化层生长牺牲氧化层生长牺牲氧化层生长厚度约25nm用来捕获Si表面的缺陷20Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well除去牺牲氧化层除去牺牲氧化层HF溶液湿法刻蚀剩下洁净的Si表面21Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Gate Oxide栅氧化层生长栅氧化层生长工艺中最关键的一步厚度210nm要求非常洁净，厚度精确(1)用作晶体管的栅绝缘层22Silicon Substrate P+Silicon
9、Epi Layer P-P-WellN-WellPolysilicon多晶硅淀积多晶硅淀积厚度150300nm化学气相淀积(CVD)23Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistChannel LengthPolysilicon光刻胶成形光刻胶成形工艺中最关键的图形转移步骤栅长的精确性是晶体管开关速度的首要决定因素使用最先进的曝光技术深紫外光(DUV)光刻胶厚度比其他步骤薄24Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistChann
10、el Length多晶硅刻蚀多晶硅刻蚀基于氟的反应离子刻蚀(RIE)必须精确的从光刻胶得到多晶硅的形状25Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Gate Oxide Poly Gate Electrode除去光刻胶26Trench OxideN-WellP-WellCross SectionPolysilicon平面视图完成栅极27Silicon Substrate P+Silicon Epi Layer P-P-WellN-Well Gate Oxide Poly Gate Electrode Poly Re-oxidati
11、on多晶硅氧化多晶硅氧化在多晶硅表面生长薄氧化层用于缓冲隔离多晶硅和后续步骤形成的Si3N428Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresist光刻胶成形光刻胶成形用于控制NMOS管的衔接注入29Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistArsenic(-)IonsN TipNMOS管衔接注入NMOS管衔接注入低能量、浅深度、低掺杂的砷离子注入衔接注入用于削弱栅区的热载流子效应30Silicon Substrate P+Silicon
12、 Epi Layer P-P-WellN-WellN Tip除去光刻胶31Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistN Tip光刻胶成形光刻胶成形用于控制PMOS管的衔接注入32Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistBF2(+)IonsN TipP TipPMOS管衔接注入低能量、浅深度、低掺杂的BF2+离子注入衔接注入用于削弱栅区的热载流子效应PMOS管衔接注入33Silicon Substrate P+Silicon E
13、pi Layer P-P-WellN-WellN TipP Tip除去光刻胶34Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellSilicon NitrideThinner HereThicker HereN TipP TipP TipSi3N4淀积Si3N4淀积厚度120180nmCVD35Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellSpacer SidewallN TipP TipP TipSi3N4刻蚀Si3N4刻蚀水平表面的薄层Si3N4被刻蚀，留下隔离侧墙侧墙精确定位晶
14、体管源区和漏区的离子注入RIE36Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistN TipP Tip光刻胶成形光刻胶成形用于控制NMOS管的源/漏区注入37Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellPhotoresistArsenic(-)IonsN+DrainN+SourceP TipNMOS管源/漏注入NMOS管源/漏注入浅深度、重掺杂的砷离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入38Silicon Substrate P+Sili
15、con Epi Layer P-P-WellN-WellN+DrainN+SourceP Tip除去光刻胶39Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourcePhotoresistP Tip光刻胶成形光刻胶成形用于控制PMOS管的源/漏区注入40Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellBF2(+)IonsPhotoresistN+DrainN+SourceP+SourceP+DrainPMOS管源/漏注入PMOS管源/漏注入浅深度、重掺杂的BF2
16、+离子注入，形成了重掺杂的源/漏区隔离侧墙阻挡了栅区附近的注入41Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+SourceP+DrainLightly Doped“Tips”除去光刻胶和退火除去光刻胶和退火用RTP工艺，消除杂质在源/漏区的迁移42Trench OxidePolysiliconCross SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacer平面视图完成晶体管源/漏极，电子器件形成43Silicon Substrate P+Silic
17、on Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+Source除去表面氧化物除去表面氧化物在HF溶液中快速浸泡，使栅、源、漏区的Si暴露出来44Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitaniumTi淀积Ti淀积厚度2040nm溅射工艺Ti淀积在整个晶圆表面45Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+Sou
18、rceTitanium SilicideUnreacted TitaniumTiSi2形成TiSi2形成RTP工艺，N2气氛，800在Ti和Si接触的区域，形成TiSi2其他区域的Ti没有变化称为自对准硅化物工艺(Salicide)46Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceTitanium SilicideTi刻蚀Ti刻蚀NH4OH+H2O2湿法刻蚀未参加反应的Ti被刻蚀TiSi2保留下来，形成Si和金属之间的欧姆接触47Silicon Substrate P+Sili
19、con Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG淀积硼磷硅玻璃(BPSG)淀积CVD，厚度约1umSiO2并掺杂少量硼和磷改善薄膜的流动性和禁锢污染物的性能这一层绝缘隔离器件和第一层金属48Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGBPSG抛光硼磷硅玻璃(BPSG)抛光CMP在BPSG层上获得一个光滑的表面49Silicon Substrate P+Silicon Epi Layer
20、 P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist光刻胶成形光刻胶成形用于定义接触孔(Contacts)这是一个关键的光刻步骤50Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGPhotoresist接触孔刻蚀接触孔刻蚀基于氟的RIE获得垂直的侧墙提供金属和底层器件的连接51Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+Sour
21、ceP+DrainP+SourceBPSG除去光刻胶52Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitanium NitrideTiN淀积TiN淀积厚度约20nm溅射工艺有助于后续的钨层附着在氧化层上53Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGTitanium NitrideTungsten钨淀积钨淀积CVD厚度不少于接触孔直径的一半
22、填充接触孔54Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact Plug钨抛光钨抛光CMP除去表面的钨和TiN留下钨塞填充接触孔55Trench OxidePolysiliconCross SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContact平面视图完成接触孔，多晶硅上的接触孔没有出现在剖面图上56Silicon Substrate P+Silicon Epi Layer P-P-Wel
23、lN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1Ti(200)-electromigration shuntTiN(500)-diffusion barrierAl-Cu(5000)-main conductorTiN(500)-antireflective coatingMetal1淀积第一层金属淀积(Metal1)实际上由多个不同的层组成溅射工艺57Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPS
24、GW Contact PlugMetal1Photoresist光刻胶成形光刻胶成形用于定义Metal1互连58Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1PhotoresistMetal1刻蚀Metal1刻蚀基于氯的RIE由于Metal1由多层金属组成，所以需要多个刻蚀步骤59Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+
25、SourceBPSGW Contact PlugMetal1除去光刻胶60Trench OxidePolysiliconCross SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1平面视图完成第一层互连61Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1IMD淀积金属间绝缘体(IMD)淀积未掺杂的SiO2连续的CVD和刻蚀工艺，厚度约1um填
26、充在金属线之间，提供金属层之间的绝缘隔离62Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1IMD抛光IMD抛光CMP63Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1Photoresist光刻胶成形光刻胶成形用于定义通孔(Vias)64Silicon
27、Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1PhotoresistIMD1通孔刻蚀通孔刻蚀基于氟的RIE，获得垂直的侧墙提供金属层之间的连接65Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1除去光刻胶66TungstenSilicon Substrate P+Silicon
28、 Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via PlugTiN和钨淀积TiN和钨淀积同第一层互连67Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via Plug钨和TiN抛光钨和TiN抛光同第一层互连68Trench OxidePolysiliconCross SectionN-Wel
29、lP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1Via1平面视图完成通孔69Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via PlugMetal2Metal2淀积Metal2淀积类似于Metal1厚度和宽度增加，连接更长的距离，承载更大的电流70Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+D
30、rainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1PhotoresistIMD1 W Via PlugMetal2光刻胶成形光刻胶成形相邻的金属层连线方向垂直，减小层间的感应耦合71Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1PhotoresistIMD1 W Via PlugMetal2Metal2刻蚀Metal2刻蚀类似于Metal172Silicon Substrate
31、P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via PlugMetal2除去光刻胶73Trench OxidePolysiliconCross SectionN-WellP-WellN+Source/DrainP+Source/DrainSpacerContactMetal1Via1Metal2平面视图完成第二层互连，后面的剖面图将包括右上角的压焊点74Silicon Substrate P+Silicon Epi Layer P-P-WellN-W
32、ellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via PlugPassivationMetal2钝化层淀积钝化层淀积多种可选的钝化层，Si3N4、SiO2和聚酰亚胺等保护电路免受刮擦、污染和受潮等75Silicon Substrate P+Silicon Epi Layer P-P-WellN-WellN+DrainN+SourceP+DrainP+SourceBPSGW Contact PlugMetal1IMD1 W Via PlugPassivationBond PadPoly GateGate Oxide
33、SilicideSpacerMetal2钝化层成形钝化层成形压焊点打开，提供外界对芯片的电接触76Cross SectionTrench OxideN+Source/DrainP+Source/DrainSpacerContactMetal1PolysiliconVia1+5V SupplyVOUTN-WellP-WellMetal2GroundBond PadVIN平面视图完成，显示了电气连接和部分压焊点77完成78略有不同的另一个工艺流程Vth校正注入场氧化层TiN79此课件下载可自行编辑修改，仅供参考！此课件下载可自行编辑修改，仅供参考！感谢您的支持，我们努力做得更好！谢谢感谢您的支持，我们努力做得更好！谢谢