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1、Copyright 2012 ARM.All rights reserved.ARM DDI 0484C(ID011713)Cortex-M0+Revision:r0p1Technical Reference Manual ARM DDI 0484CCopyright 2012 ARM.All rights reserved.iiID011713Non-ConfidentialCortex-M0+Technical Reference ManualCopyright 2012 ARM.All rights reserved.Release InformationThe following ch
2、anges have been made to this book.Proprietary NoticeWords and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries,except as otherwise stated below in this proprietary notice.Other brands and names mentioned herein may be the trademarks of their respectiv
3、e owners.Neither the whole nor any part of the information contained in,or the product described in,this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous develop
4、ments and improvements.All particulars of the product and its use contained in this document are given by ARM in good faith.However,all warranties implied or expressed,including but not limited to implied warranties of merchantability,or fitness for purpose,are excluded.This document is intended onl
5、y to assist the reader in the use of the product.ARM shall not be liable for any loss or damage arising from the use of any information in this document,or any error or omission in such information,or any incorrect use of the product.Where the term ARM is used it means“ARM or any of its subsidiaries
6、 as appropriate”.Confidentiality StatusThis document is Non-Confidential.The right to use,copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.Product StatusThe infor
7、mation in this document is final,that is for a developed product.Web Addresshttp:/Change historyDateIssueConfidentialityChange19 January 2012AConfidentialFirst release for r0p004 April 2012BNon-ConfidentialSecond release for r0p016 December 2012CNon-ConfidentialFirst release for r0p1ARM DDI 0484CCop
8、yright 2012 ARM.All rights reserved.iiiID011713Non-ConfidentialContentsCortex-M0+Technical Reference ManualPrefaceAbout this book.viFeedback.ixChapter 1Introduction1.1About the processor.1-21.2Features.1-31.3Interfaces.1-41.4Configurable options.1-51.5Product documentation,design flow and architectu
9、re.1-61.6Product revisions.1-9Chapter 2Functional Description2.1About the functions.2-22.2Interfaces.2-4Chapter 3Programmers Model3.1About the programmers model.3-23.2Modes of operation and execution.3-33.3Instruction set summary.3-43.4Memory model.3-83.5Processor core registers summary.3-93.6Except
10、ions.3-10Chapter 4System Control4.1About system control.4-24.2System control register summary.4-3ContentsARM DDI 0484CCopyright 2012 ARM.All rights reserved.ivID011713Non-ConfidentialChapter 5Nested Vectored Interrupt Controller5.1About the NVIC.5-25.2NVIC register summary.5-3Chapter 6Memory Protect
11、ion Unit6.1About the MPU .6-26.2MPU register summary.6-3Chapter 7Debug7.1About debug.7-27.2Debug register summary.7-7Appendix ARevisionsARM DDI 0484CCopyright 2012 ARM.All rights reserved.vID011713Non-ConfidentialPrefaceThis preface introduces the Cortex-M0+Technical Reference Manual.It contains the
12、 following sections:About this book on page viFeedback on page ix.Preface ARM DDI 0484CCopyright 2012 ARM.All rights reserved.viID011713Non-ConfidentialAbout this bookThis book is for the Cortex-M0+processor.Product revision statusThe rnpn identifier indicates the revision status of the product desc
13、ribed in this book,where:rn Identifies the major revision of the product.pn Identifies the minor revision or modification status of the product.Intended audienceThis book is written for:system designers,system integrators,and verification engineers software developers who want to use the processor.U
14、sing this bookThis book is organized into the following chapters:Chapter 1 Introduction Read this chapter for an introduction to the processor and its features.Chapter 2 Functional Description Read this chapter for a functional overview of the processor functions.Chapter 3 Programmers Model Read thi
15、s chapter for an overview of the application-level programmers model.Chapter 4 System Control Read this chapter for a summary of the system control registers and their structure.Chapter 5 Nested Vectored Interrupt Controller Read this chapter for a summary of the Nested Vectored Interrupt Controller
16、(NVIC).Chapter 6 Memory Protection Unit Read this chapter for a description of the Memory Protection Unit(MPU).Chapter 7 Debug Read this chapter for a summary of the debug system.Appendix A Revisions Read this for a description of the technical changes between released issues of this book.GlossaryTh
17、e ARM Glossary is a list of terms used in ARM documentation,together with definitions for those terms.The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.See ARM Glossary,http:/ ARM DDI 0484CCopyright 2012 ARM.All righ
18、ts reserved.viiID011713Non-ConfidentialConventionsThis book uses the conventions that are described in:Typographical conventions.Typographical conventionsThe following table describes the typographical conventions:Additional readingThis section lists publications by ARM and by third parties.See Info
19、center,http:/,for access to ARM documentation.ARM publicationsThis book contains information that is specific to this product.See the following documents for other relevant information:ARMv6-M Architecture Reference Manual(ARM DDI 0419).ARMv6-M Instruction Set Quick Reference Guide(ARM QRC 0011).ARM
20、 AMBA 3 AHB-Lite Protocol Specification(ARM IHI 0033).ARM Debug Interface v5,Architecture Specification(ARM IHI 0031).Note A Cortex-M0+implementation can include a Debug Access Port(DAP).This DAP is defined in v5.1 of the ARM Debug interface specification,or in the errata document to Issue A of the
21、ARM Debug Interface v5 Architecture Specification.Application Binary Interface for the ARM Architecture(The Base Standard)(IHI 0036).CoreSight SoC Technical Reference Manual(ARM DDI 0480).Cortex-M0+Integration and Implementation Manual(ARM DII 0278).CoreSight MTB-M0+Technical Reference Manual(ARM DD
22、I 0486).StylePurposeitalicIntroduces special terminology,denotes cross-references,and citations.boldHighlights interface elements,such as menu names.Denotes signal names.Also used for terms in descriptive lists,where appropriate.monospaceDenotes text that you can enter at the keyboard,such as comman
23、ds,file and program names,and source code.monospaceDenotes a permitted abbreviation for a command or option.You can enter the underlined text instead of the full command or option name.monospace italicDenotes arguments to monospace text where the argument is to be replaced by a specific value.monosp
24、ace boldDenotes language keywords when used outside example code.Encloses replaceable terms for assembler syntax where they appear in code or code fragments.For example:MRC p15,0,SMALL CAPITALSUsed in body text for a few terms that have specific technical meanings,that are defined in the ARM glossar
25、y.For example,IMPLEMENTATION DEFINED,IMPLEMENTATION SPECIFIC,UNKNOWN,and UNPREDICTABLE.Preface ARM DDI 0484CCopyright 2012 ARM.All rights reserved.viiiID011713Non-ConfidentialOther publicationsThis section lists relevant documents published by third parties:IEEE Standard,Test Access Port and Boundar
26、y-Scan Architecture specification 1149.1-1990(JTAG).Preface ARM DDI 0484CCopyright 2012 ARM.All rights reserved.ixID011713Non-ConfidentialFeedbackARM welcomes feedback on this product and its documentation.Feedback on this productIf you have any comments or suggestions about this product,contact you
27、r supplier and give:The product name.The product revision or version.An explanation with as much information as you can provide.Include symptoms and diagnostic procedures if appropriate.Feedback on contentIf you have comments on content then send an e-mail to .Give:The title.The number,ARM DDI 0484C
28、.The page numbers to which your comments apply.A concise explanation of your comments.ARM also welcomes general suggestions for additions and improvements.Note ARM tests the PDF only in Adobe Acrobat and Acrobat Reader,and cannot guarantee the quality of the represented document when used with any o
29、ther PDF reader.ARM DDI 0484CCopyright 2012 ARM.All rights reserved.1-1ID011713Non-ConfidentialChapter 1 IntroductionThis chapter introduces the Cortex-M0+processor and its features.It contains the following sections:About the processor on page 1-2.Features on page 1-3.Interfaces on page 1-4.Configu
30、rable options on page 1-5.Product documentation,design flow and architecture on page 1-6.Product revisions on page 1-9.Introduction ARM DDI 0484CCopyright 2012 ARM.All rights reserved.1-2ID011713Non-Confidential1.1About the processorThe Cortex-M0+processor is a very low gate count,highly energy effi
31、cient processor that is intended for microcontroller and deeply embedded applications that require an area optimized,low-power processor.Introduction ARM DDI 0484CCopyright 2012 ARM.All rights reserved.1-3ID011713Non-Confidential1.2FeaturesThe processor features and benefits are:Tight integration of
32、 system peripherals reduces area and development costs.Thumb instruction set combines high code density with 32-bit performance.Support for single-cycle I/O access.Power control optimization of system components.Integrated sleep modes for low power consumption.Fast code execution enables running the
33、 processor with a slower clock or increasing sleep mode time.Optimized code fetching for reduced flash and ROM power consumption.Hardware multiplier.Deterministic,high-performance interrupt handling for time-critical applications.Deterministic instruction cycle timing.Support for system level debug
34、authentication.Serial Wire Debug reduces the number of pins required for debugging.Support for optional instruction trace.For information about Cortex-M0+architectural compliance,see the Architecture and protocol information on page 1-7.Introduction ARM DDI 0484CCopyright 2012 ARM.All rights reserve
35、d.1-4ID011713Non-Confidential1.3InterfacesThe interfaces included in the processor for external access include:External AHB-Lite interface.Debug Access Port(DAP).Optional single-cycle I/O Port.Introduction ARM DDI 0484CCopyright 2012 ARM.All rights reserved.1-5ID011713Non-Confidential1.4Configurable
36、 optionsTable 1-1 shows the processor configurable options available at implementation time.1.4.1Configurable multiplierThe MULS instruction provides a 32-bit x 32-bit multiply that returns the least-significant 32-bits of the result.The processor can implement MULS in one of two ways:As a fast sing
37、le-cycle array.As a 32-cycle iterative multiplier.The iterative multiplier has no impact on interrupt response time because the processor abandons multiply operations to take any pending interrupt.Table 1-1 Processor configurable optionsFeatureConfigurable optionInterruptsExternal interrupts 0-32Dat
38、a endiannessLittle-endian or big-endianSysTick timerPresent or absentNumber of watchpoint comparatorsaa.Only when halting debug support is present.0,1,2Number of breakpoint comparatorsa0,1,2,3,4Halting debug supportPresent or absentMultiplierFast or small Single-cycle I/O portPresent or absentWake-u
39、p interrupt controllerSupported or not supportedVector Table Offset RegisterPresent or absentUnprivileged/Privileged supportPresent or absentMemory Protection UnitNot present or 8-regionReset all registersPresent or absentInstruction fetch width16-bit only or mostly 32-bitIntroduction ARM DDI 0484CC
40、opyright 2012 ARM.All rights reserved.1-6ID011713Non-Confidential1.5Product documentation,design flow and architectureThis section describes the processor books,how they relate to the design flow,and the relevant architectural standards and protocols.See Additional reading on page vii for more infor
41、mation about the books described in this section.1.5.1DocumentationThis section describes the documents for the processor.Technical Reference Manual The Technical Reference Manual(TRM)describes the functionality and the effects of functional options on the behavior of the processor.It is required at
42、 all stages of the design flow.The choices made in the design flow can mean that some behavior described in the TRM is not relevant.If you are programming the processor then contact:The implementer to determine:The build configuration of the implementation.What integration,if any,was performed befor
43、e implementing the processor.The integrator to determine the input configuration of the device that you are using.Integration and Implementation Manual The Integration and Implementation Manual(IIM)describes:The available build configuration options and related issues in selecting them.How to config
44、ure the Register Transfer Level(RTL)with the build configuration options.How to integrate the processor into a SoC.This includes describing the pins that the integrator must tie off to configure the macrocell for the required integration.The processes to sign off the integration and implementation o
45、f the design.The ARM product deliverables include reference scripts and information about using them to implement your design.Reference methodology documentation from your EDA tools vendor complements the IIM.The IIM is a confidential book that is only available to licensees.1.5.2Design FlowThe proc
46、essor is delivered as synthesizable RTL.Before it can be used in a product,it must go through the following processes:Implementation The implementer configures and synthesizes the RTL to produce a gate-level layout.The implementer can do synthesis and layout before integration to produce a hard macr
47、ocell,or after integration to produce a chip layout.Introduction ARM DDI 0484CCopyright 2012 ARM.All rights reserved.1-7ID011713Non-ConfidentialIntegration The integrator connects the configured design into a SoC.This includes connecting it to a memory system and peripherals.Programming This is the
48、last process.The system programmer develops the software required to configure and initialize the processor,and tests the required application software.Each process can be performed by a different party.The implementation and integration choices affect the behavior and features of the processor.For
49、MCUs,often a single design team integrates the processor before synthesizing the complete design.Alternatively,the team can synthesise the processor on its own or partially integrated,to produce a macrocell that is then integrated,possibly by a separate team.The operation of the final device depends
50、 on:Build configuration The implementer chooses the options that affect how the RTL source files are pre-processed.These options usually include or exclude logic that affects one or more of the area,maximum frequency,and function of the resulting macrocell.Configuration inputs The integrator configu