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1、KL25 Sub-Family Reference ManualDocument Number:KL25P80M48SF0RMRev.3,September 2012KL25 Sub-Family Reference Manual,Rev.3,September 20122Freescale Semiconductor,Inc.ContentsSection numberTitlePageChapter 1About This Document1.1Overview.331.1.1Purpose.331.1.2Audience.331.2Conventions.331.2.1Numbering
2、 systems.331.2.2Typographic notation.341.2.3Special terms.34Chapter 2Introduction2.1Overview.352.2Kinetis L Series.352.3KL25 Sub-Family Introduction.382.4Module functional categories.392.4.1ARM Cortex-M0+Core Modules.392.4.2System Modules.402.4.3Memories and Memory Interfaces.412.4.4Clocks.412.4.5Se
3、curity and Integrity modules.422.4.6Analog modules.422.4.7Timer modules.422.4.8Communication interfaces.432.4.9Human-machine interfaces.442.5Orderable part numbers.44Chapter 3Chip Configuration3.1Introduction.45KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.3Section
4、 numberTitlePage3.2Module to Module Interconnects.453.2.1Module to Module Interconnects.453.2.2Analog reference options.483.3Core Modules.483.3.1ARM Cortex-M0+Core Configuration.483.3.2Nested Vectored Interrupt Controller(NVIC)Configuration.513.3.3Asynchronous wake-up interrupt controller(AWIC)confi
5、guration.553.4System Modules.563.4.1SIM Configuration.563.4.2System Mode Controller(SMC)Configuration.573.4.3PMC Configuration.573.4.4Low-Leakage Wake-up Unit(LLWU)Configuration.583.4.5MCM Configuration.603.4.6Crossbar-Light Switch Configuration.613.4.7Peripheral Bridge Configuration.623.4.8DMA requ
6、est multiplexer configuration.633.4.9DMA Controller Configuration.663.4.10Computer Operating Properly(COP)Watchdog Configuration.673.5Clock Modules.703.5.1MCG Configuration.703.5.2OSC Configuration.713.6Memories and Memory Interfaces.723.6.1Flash Memory Configuration.723.6.2Flash Memory Controller C
7、onfiguration.74KL25 Sub-Family Reference Manual,Rev.3,September 20124Freescale Semiconductor,Inc.Section numberTitlePage3.6.3SRAM Configuration.753.7Analog.773.7.116-bit SAR ADC Configuration.773.7.2CMP Configuration.813.7.312-bit DAC Configuration.833.8Timers.843.8.1Timer/PWM Module Configuration.8
8、43.8.2PIT Configuration.873.8.3Low-power timer configuration.883.8.4RTC configuration.903.9Communication interfaces.913.9.1Universal Serial Bus(USB)FS Subsystem.913.9.2SPI configuration.963.9.3I2C Configuration.973.9.4UART Configuration.983.10Human-machine interfaces(HMI).993.10.1GPIO Configuration.
9、993.10.2TSI Configuration.101Chapter 4Memory Map4.1Introduction.1054.2System memory map.1054.3Flash Memory Map.1064.3.1Alternate Non-Volatile IRC User Trim Description.1064.4SRAM memory map.1074.5Bit Manipulation Engine.1074.6Peripheral bridge(AIPS-Lite)memory map.1084.6.1Read-after-write sequence a
10、nd required serialization of memory operations.1084.6.2Peripheral Bridge(AIPS-Lite)Memory Map.109KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.5Section numberTitlePage4.6.3Modules Restricted Access in User Mode.1124.7Private Peripheral Bus(PPB)memory map.112Chapter
11、 5Clock Distribution5.1Introduction.1155.2Programming model.1155.3High-Level device clocking diagram.1155.4Clock definitions.1165.4.1Device clock summary.1175.5Internal clocking requirements.1195.5.1Clock divider values after reset.1195.5.2VLPR mode clocking.1205.6Clock Gating.1215.7Module clocks.12
12、15.7.1PMC 1-kHz LPO clock.1225.7.2COP clocking.1225.7.3RTC clocking.1235.7.4LPTMR clocking.1235.7.5TPM clocking.1245.7.6USB FS OTG Controller clocking.1245.7.7UART clocking.125Chapter 6Reset and Boot6.1Introduction.1276.2Reset.1276.2.1Power-on reset(POR).1286.2.2System reset sources.1286.2.3MCU Rese
13、ts.1316.2.4Reset Pin.133KL25 Sub-Family Reference Manual,Rev.3,September 20126Freescale Semiconductor,Inc.Section numberTitlePage6.2.5Debug resets.1336.3Boot.1346.3.1Boot sources.1346.3.2FOPT boot options.1346.3.3Boot sequence.135Chapter 7Power Management7.1Introduction.1377.2Clocking Modes.1377.2.1
14、Partial Stop.1377.2.2DMA Wakeup.1387.2.3Compute Operation.1397.2.4Peripheral Doze.1407.2.5Clock Gating.1417.3Power modes.1417.4Entering and exiting power modes.1437.5Module Operation in Low Power Modes.143Chapter 8Security8.1Introduction.1498.2Flash Security.1498.3Security Interactions with other Mo
15、dules.1498.3.1Security Interactions with Debug.150Chapter 9Debug9.1Introduction.1519.2Debug Port Pin Descriptions.1519.3SWD status and control registers.1529.3.1MDM-AP Control Register.1539.3.2MDM-AP Status Register.154KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.
16、7Section numberTitlePage9.4Debug Resets.1569.5Micro Trace Buffer(MTB).1579.6Debug in Low Power Modes.1579.7Debug&Security.157Chapter 10Signal Multiplexing and Signal Descriptions10.1Introduction.15910.2Signal Multiplexing Integration.15910.2.1Port control and interrupt module features.16010.2.2Clock
17、 gating.16110.2.3Signal multiplexing constraints.16110.3Pinout.16110.3.1KL25 Signal Multiplexing and Pin Assignments.16110.3.2KL25 Pinouts.16410.4Module Signal Description Tables.16810.4.1Core Modules.16810.4.2System Modules.16910.4.3Clock Modules.16910.4.4Memories and Memory Interfaces.16910.4.5Ana
18、log.16910.4.6Timer Modules.17010.4.7Communication Interfaces.17110.4.8Human-Machine Interfaces(HMI).173Chapter 11Port control and interrupts(PORT)11.1Introduction.17511.2Overview.17511.2.1Features.175KL25 Sub-Family Reference Manual,Rev.3,September 20128Freescale Semiconductor,Inc.Section numberTitl
19、ePage11.2.2Modes of operation.17611.3External signal description.17611.4Detailed signal description.17711.5Memory map and register definition.17711.5.1Pin Control Register n(PORTx_PCRn).18311.5.2Global Pin Control Low Register(PORTx_GPCLR).18511.5.3Global Pin Control High Register(PORTx_GPCHR).18611
20、.5.4Interrupt Status Flag Register(PORTx_ISFR).18611.6Functional description.18711.6.1Pin control.18711.6.2Global pin control.18811.6.3External interrupts.188Chapter 12System integration module(SIM)12.1Introduction.19112.1.1Features.19112.2Memory map and register definition.19112.2.1System Options R
21、egister 1(SIM_SOPT1).19312.2.2SOPT1 Configuration Register(SIM_SOPT1CFG).19412.2.3System Options Register 2(SIM_SOPT2).19512.2.4System Options Register 4(SIM_SOPT4).19712.2.5System Options Register 5(SIM_SOPT5).19912.2.6System Options Register 7(SIM_SOPT7).20012.2.7System Device Identification Regis
22、ter(SIM_SDID).20212.2.8System Clock Gating Control Register 4(SIM_SCGC4).20412.2.9System Clock Gating Control Register 5(SIM_SCGC5).20612.2.10System Clock Gating Control Register 6(SIM_SCGC6).20712.2.11System Clock Gating Control Register 7(SIM_SCGC7).20912.2.12System Clock Divider Register 1(SIM_CL
23、KDIV1).210KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.9Section numberTitlePage12.2.13Flash Configuration Register 1(SIM_FCFG1).21112.2.14Flash Configuration Register 2(SIM_FCFG2).21312.2.15Unique Identification Register Mid-High(SIM_UIDMH).21312.2.16Unique Identi
24、fication Register Mid Low(SIM_UIDML).21412.2.17Unique Identification Register Low(SIM_UIDL).21412.2.18COP Control Register(SIM_COPC).21512.2.19Service COP Register(SIM_SRVCOP).21612.3Functional description.216Chapter 13System Mode Controller(SMC)13.1Introduction.21713.2Modes of operation.21713.3Memo
25、ry map and register descriptions.21913.3.1Power Mode Protection register(SMC_PMPROT).21913.3.2Power Mode Control register(SMC_PMCTRL).22113.3.3Stop Control Register(SMC_STOPCTRL).22213.3.4Power Mode Status register(SMC_PMSTAT).22313.4Functional description.22413.4.1Power mode transitions.22413.4.2Po
26、wer mode entry/exit sequencing.22713.4.3Run modes.22913.4.4Wait modes.23113.4.5Stop modes.23213.4.6Debug in low power modes.235Chapter 14Power Management Controller(PMC)14.1Introduction.23714.2Features.237KL25 Sub-Family Reference Manual,Rev.3,September 201210Freescale Semiconductor,Inc.Section numb
27、erTitlePage14.3Low-voltage detect(LVD)system.23714.3.1LVD reset operation.23814.3.2LVD interrupt operation.23814.3.3Low-voltage warning(LVW)interrupt operation.23814.4I/O retention.23914.5Memory map and register descriptions.23914.5.1Low Voltage Detect Status And Control 1 register(PMC_LVDSC1).24014
28、.5.2Low Voltage Detect Status And Control 2 register(PMC_LVDSC2).24114.5.3Regulator Status And Control register(PMC_REGSC).242Chapter 15Low-Leakage Wakeup Unit(LLWU)15.1Introduction.24515.1.1Features.24515.1.2Modes of operation.24615.1.3Block diagram.24715.2LLWU signal descriptions.24815.3Memory map
29、/register definition.24815.3.1LLWU Pin Enable 1 register(LLWU_PE1).24915.3.2LLWU Pin Enable 2 register(LLWU_PE2).25015.3.3LLWU Pin Enable 3 register(LLWU_PE3).25115.3.4LLWU Pin Enable 4 register(LLWU_PE4).25215.3.5LLWU Module Enable register(LLWU_ME).25315.3.6LLWU Flag 1 register(LLWU_F1).25515.3.7L
30、LWU Flag 2 register(LLWU_F2).25715.3.8LLWU Flag 3 register(LLWU_F3).25815.3.9LLWU Pin Filter 1 register(LLWU_FILT1).26015.3.10LLWU Pin Filter 2 register(LLWU_FILT2).26115.4Functional description.26215.4.1LLS mode.263KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.11S
31、ection numberTitlePage15.4.2VLLS modes.26315.4.3Initialization.263Chapter 16Reset Control Module(RCM)16.1Introduction.26516.2Reset memory map and register descriptions.26516.2.1System Reset Status Register 0(RCM_SRS0).26516.2.2System Reset Status Register 1(RCM_SRS1).26716.2.3Reset Pin Filter Contro
32、l register(RCM_RPFC).26816.2.4Reset Pin Filter Width register(RCM_RPFW).269Chapter 17Bit Manipulation Engine(BME)17.1Introduction.27117.1.1Overview.27217.1.2Features.27217.1.3Modes of Operation.27317.2External Signal Description.27317.3Memory Map and Register Definition.27417.4Functional Description
33、.27417.4.1BME Decorated Stores.27417.4.2BME Decorated Loads.28017.4.3Additional Details on Decorated Addresses and GPIO Accesses.28717.5Application Information.288Chapter 18Miscellaneous Control Module(MCM)18.1Introduction.29118.1.1Features.29118.2Memory map/register descriptions.29118.2.1Crossbar S
34、witch(AXBS)Slave Configuration(MCM_PLASC).29218.2.2Crossbar Switch(AXBS)Master Configuration(MCM_PLAMC).293KL25 Sub-Family Reference Manual,Rev.3,September 201212Freescale Semiconductor,Inc.Section numberTitlePage18.2.3Platform Control Register(MCM_PLACR).29318.2.4Compute Operation Control Register(
35、MCM_CPO).296Chapter 19Micro Trace Buffer(MTB)19.1Introduction.29919.1.1Overview.29919.1.2Features.30219.1.3Modes of Operation.30319.2External Signal Description.30319.3Memory Map and Register Definition.30419.3.1MTB_RAM Memory Map.30419.3.2MTB_DWT Memory Map.31619.3.3System ROM Memory Map.326Chapter
36、 20Crossbar Switch Lite(AXBS-Lite)20.1Introduction.33120.1.1Features.33120.2Memory Map/Register Definition.33120.3Functional Description.33220.3.1General operation.33220.3.2Arbitration.33320.4Initialization/application information.334Chapter 21Peripheral Bridge(AIPS-Lite)21.1Introduction.33521.1.1Fe
37、atures.33521.1.2General operation.33521.2Functional description.33621.2.1Access support.336KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semiconductor,Inc.13Section numberTitlePageChapter 22Direct Memory Access Multiplexer(DMAMUX)22.1Introduction.33722.1.1Overview.33722.1.2Features.
38、33822.1.3Modes of operation.33822.2External signal description.33922.3Memory map/register definition.33922.3.1Channel Configuration register(DMAMUXx_CHCFGn).33922.4Functional description.34022.4.1DMA channels with periodic triggering capability.34122.4.2DMA channels with no triggering capability.343
39、22.4.3Always-enabled DMA sources.34322.5Initialization/application information.34422.5.1Reset.34422.5.2Enabling and configuring sources.344Chapter 23DMA Controller Module23.1Introduction.34923.1.1Overview.34923.1.2Features.35023.2DMA Transfer Overview.35123.3Memory Map and Registers.35223.3.1Source
40、Address Register(DMA_SARn).35323.3.2Destination Address Register(DMA_DARn).35423.3.3DMA Status Register/Byte Count Register(DMA_DSR_BCRn).35523.3.4DMA Control Register(DMA_DCRn).35723.4Functional Description.36123.4.1Transfer Requests(Cycle-Steal and Continuous Modes).361KL25 Sub-Family Reference Ma
41、nual,Rev.3,September 201214Freescale Semiconductor,Inc.Section numberTitlePage23.4.2Channel Initialization and Startup.36123.4.3Dual-Address Data Transfer Mode.36323.4.4Advanced Data Transfer Controls:Auto-Alignment.36423.4.5Termination.365Chapter 24Multipurpose Clock Generator(MCG)24.1Introduction.
42、36724.1.1Features.36724.1.2Modes of Operation.37024.2External Signal Description.37124.3Memory Map/Register Definition.37124.3.1MCG Control 1 Register(MCG_C1).37224.3.2MCG Control 2 Register(MCG_C2).37324.3.3MCG Control 3 Register(MCG_C3).37424.3.4MCG Control 4 Register(MCG_C4).37424.3.5MCG Control
43、5 Register(MCG_C5).37624.3.6MCG Control 6 Register(MCG_C6).37724.3.7MCG Status Register(MCG_S).37824.3.8MCG Status and Control Register(MCG_SC).38024.3.9MCG Auto Trim Compare Value High Register(MCG_ATCVH).38124.3.10MCG Auto Trim Compare Value Low Register(MCG_ATCVL).38124.3.11MCG Control 7 Register
44、(MCG_C7).38224.3.12MCG Control 8 Register(MCG_C8).38224.3.13MCG Control 9 Register(MCG_C9).38324.3.14MCG Control 10 Register(MCG_C10).38324.4Functional Description.38424.4.1MCG mode state diagram.38424.4.2Low Power Bit Usage.388KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semicondu
45、ctor,Inc.15Section numberTitlePage24.4.3MCG Internal Reference Clocks.38824.4.4External Reference Clock.38924.4.5MCG Fixed frequency clock.38924.4.6MCG PLL clock.39024.4.7MCG Auto TRIM(ATM).39024.5Initialization/Application information.39124.5.1MCG module initialization sequence.39124.5.2Using a 32.
46、768 kHz reference.39324.5.3MCG mode switching.394Chapter 25Oscillator(OSC)25.1Introduction.40525.2Features and Modes.40525.3Block Diagram.40625.4OSC Signal Descriptions.40625.5External Crystal/Resonator Connections.40725.6External Clock Connections.40825.7Memory Map/Register Definitions.40925.7.1OSC
47、 Memory Map/Register Definition.40925.8Functional Description.41025.8.1OSC Module States.41025.8.2OSC Module Modes.41225.8.3Counter.41325.8.4Reference Clock Pin Requirements.41325.9Reset.41425.10 Low Power Modes Operation.41425.11 Interrupts.414KL25 Sub-Family Reference Manual,Rev.3,September 201216
48、Freescale Semiconductor,Inc.Section numberTitlePageChapter 26Flash Memory Controller(FMC)26.1Introduction.41526.1.1Overview.41526.1.2Features.41526.2Modes of operation.41626.3External signal description.41626.4Memory map and register descriptions.41626.5Functional description.416Chapter 27Flash Memo
49、ry Module(FTFA)27.1Introduction.41927.1.1Features.42027.1.2Block Diagram.42027.1.3Glossary.42127.2External Signal Description.42227.3Memory Map and Registers.42227.3.1Flash Configuration Field Description.42227.3.2Program Flash IFR Map.42327.3.3Register Descriptions.42427.4Functional Description.432
50、27.4.1Flash Protection.43327.4.2Interrupts.43327.4.3Flash Operation in Low-Power Modes.43427.4.4Functional Modes of Operation.43427.4.5Flash Reads and Ignored Writes.43427.4.6Read While Write(RWW).43527.4.7Flash Program and Erase.435KL25 Sub-Family Reference Manual,Rev.3,September 2012Freescale Semi