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1、 More and more large-scale physics experiments and scientific instruments platforms need to use a variety of imaging systems, including astronomy, high energy physics, nuclear physics, such as optical band astronomical observations, the soft x-ray CCD imaging, infrared band camera , CCD-based dark m
2、atter search, etc., especially many high-energy physics and nuclear physics experiments are got benefit from the ultra-low-noise CCD readout system. Currently, PCs have USB3.0 interface with its maximum data transmission rate-5Gbps. The imaging controller is connected to a PC via the USB3.0 directly
3、 that is suitable for stand-alone version imaging system as shown in Fig.1. In a large scale imaging system as shown in Fig.2, the cameras are integrated into the high-speed data processing and control module through optical interface. And the optical fiber takes advantage of long-distance transmiss
4、ion, low loss, easy expansion and networking. The structure of CCD imaging controller, as shown in Fig.3, is designed as several plug-in boards connected by CPCI mother board. Fig.1 CCD Camera Basic Block Diagram Fig.2 Large-scale Remote CCD Imaging Integrated System As a generic design as shown in
5、Fig.3, the plug-in boards are designed to 3 kinds that are master board which provide data transmission interface, data storage, clock & bias generating control, data processing etc; clock & bias board which generating clock & bias signals for CCD chip; data acquisition board which read out the pixe
6、l data from CCD chip. The master board as a control hub for CCD imaging controller is responsible for communication with the host computer by USB3.0 interface or optical fiber interface. Fig 3. CCD Imaging Controller Structure Diagram2.USB3.0 Communication Design4.ConclusionsGeneric Design of Master
7、 Board of CCD Controller for Antarctic Astronomical Science Imaging SystemSheng-zhao LIN1,2, Hong-fei ZHANG1,2, Ke CUI1,2, Jian-min WANG1,2, Xiao-fei DONG1,2, Jie CHEN1,2, Jian WANG1,2( 1.Anhui Key Laboratory of Physical Electronics, Modern Physics Department, University of Science and Technology of
8、 China2.State Key Laboratory of Technologies of Particle Detection and Electronics, Hefei, Anhui, 230026Email: )Bibliography The design of USB3.0 communication module, as shown in Fig.4, includes hardware design, firmware design, FPGA logic design and PC software design. The USB transceiver uses Cyp
9、resss CY7CUSB3014 1-3 USB3.0 ultra-high-speed chip. Fig.4 Diagram of USB3.0 communication structure EZ-USB FX3 has a fully configurable parallel, general programmable interface, called GPIF II, which can connect to an external processor, ASIC, or FPGA. A popular implementation of GPIF II is the sync
10、hronous Slave FIFO interface. The synchronous Slave FIFO interface is suitable for applications in which an external processor or device needs to perform data read/write accesses to EZ-USB FX3s internal FIFO buffers. Fig.4 shows the signals and the synchronous slave FIFO interface between FPGA and E
11、Z-USB FX3. The synchronous slave FIFO interface supports access to up to 4 sockets with 2 address or 32 sockets with 5 address. In this application, 2 sockets are used. 2-Bit address mode is shown in Fig.4. The A1:0 describe the synchronous slave FIFO interface with two address lines. The synchronou
12、s slave FIFO interface with a 2-bit address is configured using GPIF II designer. In this application, 2 sockets, 2 thread, DMA buffer size with 16Kbyte, DMA AUTO channel 32-bit data, GPIF II interface speed with 100MHz and partial FLAG are used in this firmware. 1.Cypress Semiconductor, CYUSB3014,
13、EZ-USB FX3 Super-Speed USB Controller, Document Number 001-52136 Rev. *K.2.Cypress Semiconductor, AN65974, Designing with the EZ-USB FX3 Slave FIFO Interface, Document No. 001-65974 Rev. *I.3.Cypress Semiconductor, AN75705, Getting Started with EZ-USB FX3, Document No. 001-75705 Rev. *C.4.XILINX, Sp
14、artan-6 FPGA GTP Transceivers Advance Product Specification, UG386 (v2.2) April 30, 2010.5.XILINX, LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard v1.11 User Guide, UG546 (v1.11) October 19, 2011. In the optical fiber interface as shown in Fig.6, the internal SERDES of FPGA chip is used . Spartan6
15、 4 series XC6SLX75T type FPGA is used in the master board, which has a high-speed serial transceiver - GTP transceiver. A dedicated clock chip is used to configure the GTP transceiver clock frequency. Different clock frequencies, high-speed communication rate will be changed with different configura
16、tion, and the maximum rate can be reached to 2.45Gb/s to 3.125Gb/s. SFP transceiver modules use differential signal pair and FPGA GTP dedicated I/O. XILINX CORE Generator tool is used for GTP IP Core 5 configuration including setting rate, reference clock, 8B/10B coding, data width, the alignment ma
17、rk and other parameters. Fig. 6 Schematic of optical fiber communicationTests on the prototype as shown in Fig.7 show that the scientific grade CCD imaging system master board based on high-speed serial bus can meet the high-speed transmission, high integration, requirements for different distances,
18、 scalability. It has beneficial for practical system with integration, miniaturization and remote control.Fig.7 CCD Master Controller Prototype 1.Introduction3. Optical Fiber Communication Design The USB3.0 logic of FPGA includes USB interface module and USB command module. The interface module tran
19、smits or receives USB data with 32-bit width. Command module parses USB command if needs. The logic state machine is designed for read and write. The state machine switches between the read address and write address periodically, and then judges the FLAG. The development of USB3.0 PC Software is bas
20、ed on cyusb3.sys driven, and use the Cypress CyAPI.lib which provides a high-level programming interface to the CyUsb3.sys kernel mode driver. The USB PC software graphical user interface as shown in Fig.5. The Throughput with 241.395MByte/s is currently displayed. Fig.5 USB PC Software Graphical User Interface