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1、2009AlteraCorporation1Quartus II Software Design Series:Timing Analysis-Timing analysis basicsTiming analysis basics2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation2ObjectivesnDisplayacompleteunderstandingoftiminganalysis2009Alte
2、raCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation3How does timing verification work?nEverydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirements-Catchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boar
3、dtestingnDesignermustentertimingrequirements&exceptions-Usedtoguidefitterduringplacement&routing-UsedtocompareagainstactualresultsINCLKOUTDQCLRPREDQCLRPREcombinationaldelaysCLR2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation4Timi
4、ng Analysis BasicsnLaunchvs.latchedgesnSetup&holdtimesnData&clockarrivaltimenDatarequiredtimenSetup&holdslackanalysisnI/OanalysisnRecovery&removalnTimingmodels2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation5Path&Analysis TypesTh
5、reetypesofPaths:1.ClockPaths2.DataPath3.AsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:1.Synchronousclock&datapaths2.Asynchronous*clock&asyncpaths*Asynchronous refers to signals feeding the asynchronous control ports of the registers2009AlteraCorporationAlte
6、ra,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation6Launch&Latch EdgesCLKLaunch Launch EdgeEdgeLatch Latch EdgeEdgeDataValidDATALaunchEdge:theedgewhich“launches”thedatafromsourceregisterLatchEdge:theedgewhich“latches”thedataatdestinationregister(withrespect
7、tothelaunchedge,selectedbytiminganalyzer;typically1cycle)2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation7Setup&HoldSetup:TheminimumtimedatasignalmustbestableBEFOREclockedgeHold:TheminimumtimedatasignalmustbestableAFTERclockedgeD
8、QCLRPRECLKThValidDATATsuCLKDATATogether,the setup time and hold time form a Data Required Window,the time around a clock edge in which data must be stable.2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation8Data Arrival TimeDataArri
9、valTime=launchedge+Tclk1+Tco+TdataCLKREG1.CLKTclk1DataValidREG2.DTdataLaunchEdgeDataValidREG1.QTconThetimefordatatoarriveatdestinationregistersDinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdata2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAl
10、teraCorporation9Clock Arrival TimeClockArrivalTime=latchedge+Tclk2CLKREG2.CLKTclk2LatchEdgenThetimeforclocktoarriveatdestinationregistersclockinputREG1PREDQCLRREG2PREDQCLRComb.LogicTclk22009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorpor
11、ation10Data Required Time-SetupDataRequiredTime=ClockArrivalTime-Tsu-SetupUncertaintyCLKREG2.CLKTclk2LatchEdgenTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterTsuDataValidREG2.DDatamustbevalidhereREG1PREDQCLRREG2PREDQCLRComb.LogicTclk2Tsu2009AlteraCorporationAltera,Stratix,Arri
12、a,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation11Data Required Time-HoldDataRequiredTime=ClockArrivalTime+Th+HoldUncertaintyCLKREG2.CLKTclk2LatchEdgenTheminimumtimerequiredforthedatatogetlatchedintothedestinationregisterThDatamustremainvalidtohereDataValidREG2.DREG1PR
13、EDQCLRREG2PREDQCLRComb.LogicTclk2Th2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation12Tclk2Setup SlackREG2.CLKnThemarginbywhichthesetuptimingrequirementismet.Itensureslauncheddataarrivesintimetomeetthelatchingrequirement.TsuCLKREG
14、1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTco Setup SlackLaunchEdgeLatchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Tsu2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation13Setup Slack(contd)Positiveslack-Timingrequire
15、mentmetNegativeslack-TimingrequirementnotmetSetup Slack=Data Required Time Data Arrival Time2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation14Hold SlackREG2.CLKTclk2nThemarginbywhichtheholdtimingrequirementismet.Itensureslatchdat
16、aisnotcorruptedbydatafromanotherlaunchedge.ThCLKREG1.CLKTclk1DataValidREG2.DTdataDataValidREG1.QTcoHoldSlackLatchEdgeNextLaunchEdgeREG1PREDQCLRREG2PREDQCLRComb.LogicTclk1TCOTdataTclk2Th2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorpora
17、tion15Hold Slack(contd)Positiveslack-TimingrequirementmetNegativeslack-TimingrequirementnotmetHold Slack=Data Arrival Time Data Required Time2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation16FPGA/CPLD or ASSPASSP or FPGA/CPLDI/O
18、Analysis nAnalyzingI/Operformanceinasynchronousdesignusesthesameslackequations-Mustincludeexternaldevice&PCBtimingparametersreg1PREDQCLRreg2PREDQCLRCL*TdataTclk1Tclk2TCOTsu/ThOSCDataArrivalPathDataArrivalPathDataRequiredPath*Represents delay due to capacitive loading2009AlteraCorporationAltera,Strat
19、ix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation17Recovery&RemovalRecovery:TheminimumtimeanasynchronoussignalmustbestableBEFOREclockedgeRemoval:TheminimumtimeanasynchronoussignalmustbestableAFTERclockedgeDQCLRSETCLKTremValidASYNCTrecCLKASYNC2009AlteraCorporation
20、Altera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation18Asynchronous=Synchronous?nAsynchronouscontrolsignalsourceisassumedsynchronous-Slackequationsstillapplyldataarrivalpath=asynchronouscontrolpathlTsuTrec;ThTrem-Externaldevice&boardtimingparametersmayben
21、eeded(Ex.1)ASSPreg1PREDQCLRFPGA/CPLDreg2PREDQCLROSCFPGA/CPLDreg1PREDQCLRreg2PREDQCLRExample1Example2Data arrival pathData arrival pathData required pathData required path2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation19Why Are T
22、hese Calculations Important?nCalculationsareimportantwhentimingviolationsoccur-NeedtobeabletounderstandcauseofviolationnExamplecauses-Datapathtoolong-Requirementtooshort(incorrectanalysis)-Largeclockskewsignifyingagatedclock,etc.nTimeQuesttiminganalyzerusesthem-Equationstocalculateslack-Terminology(
23、launchandlatchedges,DataArrivalPath,DataRequiredPath,etc.)intimingreports2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation20Timing Models in DetailnQuartusIIsoftwaremodelsdevicetimingattwoPVTconditionsbydefault-Slow CornerModellIn
24、dicatesslowestpossibleperformanceforanysinglepathlTimingforslowestdeviceatmaximumoperatingtemperatureandVCCMIN-Fast CornerModellIndicatesfastestpossibleperformanceforanysinglepathlTimingforfastestdeviceatminimumoperatingtemperatureandVCCMAXnWhytwocornertimingmodels?-Ensuresetuptimingismetinslowmodel
25、-EnsureholdtimingismetinfastmodellEssentialforsourcesynchronousinterfacesnThirdmodel(slow,min.temp.)availableonlyfor65nmandsmallertechnologydevices(temperatureinversionphenomenon)2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation21
26、Generating Fast/Slow NetlistnSpecifyoneofthedefaulttimingmodelstobeusedwhencreatingyournetlistnDefaultistheslowtimingnetlistnTospecifyfasttimingnetlist-Use-fast_modeloptionwithcreate_timing_netlistcommand-ChooseFast cornerinGUIwhenexecutingCreate Timing NetlistfromNetlistmenu-CANNOTselectfastcornerf
27、romTasksPane2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation22Specifying Operating Conditions nPerformtiminganalysisfordifferentdelaymodelswithoutrecreatingtheexistingtimingnetlistnTakesprecedenceoveralreadygeneratednetlistnRequi
28、redforselectingslow,min.temp.modelandothermodels(industrial,military,etc.)dependingondevicenUseget_available_operating_conditionstoseeavailableconditionsfortargetdevice2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporationReference Doc
29、umentsReference DocumentsnQuartusIIHandbook,Volume3,Chapter7TheQuartusIITimeQuestTimingAnalyzerhttp:/ DocumentsReference DocumentsnSDCandTimeQuestAPIReferenceManual-http:/ TrainingWithAlterasinstructor-ledtrainingcourses,youcan:ListentoalecturefromanAlteratechnicaltrainingengineer(instructor)Complet
30、ehands-onexerciseswithguidancefromanAlterainstructorAskquestions&receivereal-timeanswersfromanAlterainstructorEachinstructor-ledclassisoneortwodaysinlength(8workinghoursperday).Online TrainingWithAlterasonlinetrainingcourses,youcan:TakeacourseatanytimethatisconvenientforyouTakeacoursefromthecomforto
31、fyourhomeoroffice(noneedtotravelaswithinstructor-ledcourses)Eachonlinecoursewilltakeapproximateonetothreehourstocomplete.http:/ More Through Technical Training2009AlteraCorporationAltera,Stratix,Arria,Cyclone,MAX,HardCopy,Nios,Quartus,andMegaCorearetrademarksofAlteraCorporation26Altera Technical SupportnReferenceQuartusIIsoftwareon-linehelpnQuartusIIHandbooknConsultAlteraapplications(factoryapplicationsengineers)-MySupport:http:/