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1、Chapter 7: FET Biasing1) A JFET can be biased in several different ways. The common method(s) of biasing an n-channel JFET is(are) _. A) self-bias configuration B) voltage-divider bias configuration C) fixed-bias configuration D) All of the above 2) In a self-bias circuit for an n-channel JFET trans
2、istor the se1f-bias line _. A) is straight up and down parallel to the ID axis B) is straight left and right parallel to the VGS axis C) is slanted and passing through the ID and the VGS axis on the positive side D) is slanted and passes through origin 3) In a self-bias circuit for an n-channel JFET
3、 transistor the se1f-bias line _. A) is straight up and down parallel to the ID axis B) is straight left and right parallel to the VGS axis C) is slanted and passing through the ID and the VGS axis on the positive side D) is slanted and passes through origin 4) In a fixed-bias circuit for an n-chann
4、el JFET transistor the bias line _. A) is straight up and down parallel to the ID axis B) is straight left and right parallel to the VGS axis C) is slanted and passing through the ID and the VGS axis on the positive side D) is slanted and passes through origin 5) Calculate the quiescent drain curren
5、t and the gate-to-source voltage for this voltage-divider bias circuit. A) IDQ = 2.4 mA and VGSQ = 1.8 V B) IDQ = 2.4 mA and VGSQ Q = -1.8 V C) IDQ = 1.2 mA and VGSQ Q = -3.6 V D) IDQ = 1.2 mA and VGSQ Q = 3.6 V 6) Calculate the drain-gate voltage for this voltage-divider bias circuit. A) VDG = 8.42
6、 V B) VDG = 7.42 V C) VDG = 6.42 V D) VDG = 5.42 V 7) Calculate the quiescent drain current for this self-bias depletion mode MOSFET transistor amplifier. A) IDQ = 1.9 mA B) IDQ = 1.7 mA C) IDQ = 1.5 mA D) IDQ = 1.3 mA 8) In the enhancement type of MOSFET the channel is formed when the gate-to-sourc
7、e voltage _. A) exceeds the pinch-off voltage B) is less than the pinch-off voltage C) is less than the threshold voltage D) exceeds the threshold voltage 9) Calculate the quiescent drain current for this circuit. A) IDQ = 2.5 mA B) IDQ = 2.9 mA C) IDQ = 3.3 mA D) IDQ = 3.7 mA 10) Calculate the quie
8、scent collector current for this circuit. A) ICQ = 1.7 mA B) ICQ = 1.9 mA C) ICQ = 2.1 mA D) ICQ = 2.3 mA 11) Calculate the quiescent collector-to-emitter voltage for the BJT in this circuit. A) VCE = 3.63 V B) VCE = 7.78 V C) VCE = -4.14 V D) VCE = 5.11 V 12) Calculate the voltage at the drain of t
9、he JFET in this combination network. A) VD = 8.22 V B) VD = 4.14 V C) VD = 12.5 V D) VD = 3.5 V 13) Generally, it is a good design practice for linear amplifiers to choose the operating point that is approximately _. A) near the saturation region B) near the cut-off region C) in the center of the ac
10、tive region D) near the origin 14) The analysis that we mostly work with is that of the n-channel device. For p-channel devices the transfer curve employed is the _ image and the defined current directions are _. A) identical; the same B) mirror; the same C) mirror; reversed D) identical; reversed 1
11、5) It is important to remember that when the JFET is used as a voltage variable resistor, which is one of its practical applications, the voltage VDS is _ VDS(max) and | VGS | is _ |VP|. A) very much greater than; very much greater than B) very much less than; very much greater than C) very much gre
12、ater than; very much less than D) very much less than; very much less than 16) The simplest biasing arrangement for the n-channel JFET is _. A) voltage-divider bias B) variable bias C) drain-feedback bias D) fixed bias 17) The fixed-bias technique requires _ power supplies. A) 1 B) 2 C) 3 D) 4 18) A
13、 JFET has the following ratings: VP = -2 V to -5 V and an IDSS = 4 mA. The device is being used in a fixed-bias circuit with a gate supply voltage of VGG = 1 V. What is the difference between the minimum and maximum values of ID values for the circuit? A) 7.6 mA B) 9.6 mA C) 6.68 mA D) 8.6 mA 19) Th
14、e self-bias configuration develops the controlling gate-to-source voltage across a resistor introduced in the _. A) drain leg B) gate leg C) source leg D) None of the above 20) A characteristic of voltage divider-bias in FET circuits is _. A) the current in both R1 and R2 is the same B) the voltage
15、drop across R2 is VGS C) the gate current is zero D) All of the above 21) When using voltage divider-bias in FET amplifiers, increasing the size of the source resistor results in _. A) lower quiescent values B) more positive of VGS C) a larger value of drain current D) All of the above 22) The prima
16、ry difference between JFETs and depletion-type MOSFETs is _. A) JFETs can have positive values of VGS and levels of drain current that exceed IDSS B) depletion-type MOSFETs can have positive values of VGS and levels of ID that exceed IDSS C) depletion-type MOSFETs can have only positive of VGS D) JF
17、ETs can have only positive values of VGS 23) _ biasing may be used with D-MOSFETs but not with JFETs. A) Gate-drain B) Zero C) Gate-cutoff D) Current-source 24) A popular arrangement for enhancement type MOSFET biasing is _. A) drain-feedback biasing B) fixed bias C) source-resistor bias D) All of t
18、he above 25) An E-MOSFET has values of VGSth = 2 V and IDON = 8 mA when VFS = 10 V. What is the value of k for the device? A) 0.0001 B) 0.000125 C) 80 D) Cannot be determined from the information given 26) An E-MOSFET has values of VGSth = 4 V and IDON = 12 mA when VGS = 10 V. The device is being us
19、ed in a circuit that has a value of VGS = 6 V. What is the value of ID for the circuit? A) 13.33 mA B) 1 mA C) 1.33 m D) 0 mA 27) Which of the following biasing circuits can be used with E-MOSFETs? A) self bias B) zero bias C) drain-feedback bias D) current-source bias 28) Generally, it is good desi
20、gn practice for linear amplifiers to have operating points that close to _. A) are close to saturation level B) the cut-off region C) the midpoint of the load line D) None of the above 29) This graphical solution represents _. A) voltage-divider bias for an n-channel JFET B) self bias for an n-chann
21、el JFET C) fixed-bias configuration for an n-channel JFET. D) None of the above 30) This graphical solution represents _. A) fixed bias for an n-channel JFET B) voltage-divider bias for an n-channel JFET C) self bias for an n-channel JFET D) None of the above 31) Which of the following is true for t
22、his circuit? A) VG is measured between the gate and common. B) VG is measured between the gate and source terminals. C) VG is equal to the voltage across RS. D) VG is always close to +0.7 V. 32) Which one of the following statements about this circuit is true? A) VGS is measured across R2. B) VGS is
23、 measured between the gate and source terminals. C) VGS is equal to the voltage across RS. D) VGS is always close to +0.7 V. 33) Which of the following equations properly characterize the value of VDS for this circuit? A) VDS = VD - VS B) VDS = VDD - ID(RD + RS) C) VDS = VR1 + VR2 - ID(RD + RS) D) A
24、ll of the above 34) Which of the following expressions is correct for this circuit? A) VGS = VG - ID RS B) VGS = VG - IS RS C) VGS = VG - VS D) All of the above ANSWER KEY: Chapter 7: FET Biasing - Answer Key 1) D 2) D 3) D 4) A 5) B 6) A 7) B 8) D 9) C 10) A 11) D 12) C 13) C 14) C 15) D 16) D 17) B 18) C 19) C 20) D 21) A 22) B 23) B 24) A 25) B 26) C 27) C 28) C 29) C 30) B 31) A 32) B 33) D 34) D