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1、WAT Parameters ReviewSpeaker:Alan Huang1FlowWhy WAT?WAT Parameter Review.1)Process test Methodology.2)Device test Methodology.3)Process Factor Influence on WAT Para.4)WAT Application5)General Guide-line when WAT fail6)Example introduce2 Why WAT?Debug the Process Error.Monitor Process Window.Check De
2、sign Rule.Control the Process Parameters(SPC).Reliability Characterization.Device Modeling for Circuit Design.Develop next Generation.3(in=13206.24614.8)TST2TST1TST7TST3TST4TST8TST9TST5TST6(out=13326.24734.8)(0.0)frame=120 x120Test site and Test line location4WAT Parameter ReviewProcess Part:1)Spaci
3、ng(Bridge,short)2)Continuity(Open)3)Isolation4)Sheet Rs5)Contact Rc6)Kelvin Structure for Resistance7)Integrity(Inter layer dielectric)8)Extension rule check9)CD measurement10)Junction leakageDevice Part:1)Gm(Vth,Current Gain)2)Idsat(Asym)3)Ioff4)Swing5)Gamma factor6)BKV7)Isub8)Leff,Rext,Weff9)Field
4、 Device test10)Capacitance6Process Part:(1)Spacing(Bridge,short)Define：验证在Process中，同层/同层之间的隔绝能力!Measurement method：Force 1uA电流到导线上，假若线路中有short，则测量出的电压值就偏低(deplationweak 2.inversionstrong inversion,Swing既是测量weak inversion时3.Id与Vg的变化程度!(exponential)4.DIBl effect measurement:5.Step1:Vs=Vb=,Vd=and Sweep
5、 Vg6.Step2:Plot log(Ids)Vgs7.Step3:Plot Max slop of this curve on log(Ids)Vgs8.Step4:Repeat(a)but Vd=Vcc9.Step5:Repeat(b),10.PS:如果发生punch-through(Subsurface-DIBL),High drain St 11.will larger than Low drain.(Swing越大,Leakage越大)01VDS=5VVDS=0.1VVGID20Device Part:5)Gamma factor6)Define:=(2qNa1/2/Cox=Vt/
6、(2f+Vbs1)1/2 1.-(2f+Vbs2)1/2)2.Vt=Vf+2f+(2qNb(2f+Vsb)1/2/Cox3.*Gamma factor是在计算Substrate与Source4.间非等电位时，对Vt变化的影响.(Vt值需依5.Vbs的大小改变来计算)6.Measurement method:7.Step1:Fixed Vd=V8.Step2:Measure Vt under various Substate bias.9.Step3:Plot Vt versus(2f+Vbs)1/2 curve10.Step4:slope of the curve is taken to be
7、 Gammar factor.11.PS:Vt adjusment,Deep implant,well implant,12.well implant都会影响此一参数，通常Vt浓13.度越高，值越大!同理，不同的device在相5)同的Back-bias测量下，Vt差值，亦代表着1.值的影响VDVGN2N121Device Part:6)BKV7)Define:Drain voltage which produces 1uA 8)Drain Current.9)Breakdown Voltage是用来 test MOS的耐压程度。(1)在Long channel的Device，看的是S/D t
8、o well 间junction的崩溃电压(2)在Short channel的status，看到的BKV，有可 能是来自drain to source因punch-through造成 的低电压现象!PS:可籍由Id流到Is or Ib来判断BKV由何种造成！Measurement method:Step1:Vs=Vg=Vb=VStep2:set up Drain current limited at 1uA.Step3:Plot Ids VdsStep4:Sweep Vd and find the Voltage at Id=1uAN+N+VSVGVDVB22Device Part:8)Lef
9、f,Weff and Rext9)Define:Leff=Lmask-2L,Rext=Rm-1.Rchannel,Weff=Wmask-2 W2.公式推导：公式推导：3.IDS=(Weff/Leff)*Cox*n*(Vgs-Vt-0.5VDS)VDS4.Rch=VDS/IDS=Leff/(Weff*Cox*n*(Vgs-Vt-5.0.5VDS)6.Rm=Vf/Im=Rext+Rch=Rext+A(Lmask-2L)7.A=1/(Weff*Cox*n*(Vgs-Vt-0.5VDS)8.Measurement method:9.Step1:Fixed VDS=0.1V,Vb=Vs=0V10.Ste
10、p2:变化Vgs-Vt=2,3V11.Step3:Plot Rm Lmask12.Step4:选相同的Channel Width不同的length的13.device测量不同的 Vgs-Vt Bias 下的IDS,计算14.Rm=VDS/IDS15.Step5:计算两直线交点16.X轴截距=2 L(2W 算法同）17.Y轴截距=Rext 01432567Rext=1650100150200VDS=0.1VVgS=0VGS=6VVGS=8VVGS=10VVGS=12VVGS=14V24Device Part:9)Field Device test10)Define:测量Active region
11、与field oxide 所 11)形成的寄生元件之Isolation能力测 12)试！13)考虑不同的 layout结构，有以下两种测量法：14)Measurement method:(1)Field Oxide上有导电材料覆盖：(2)此结构如同一AMOS元件，MOS Vt的大(3)小，即反映出Field Isolation能力的好坏！(4)PS:测量方法同Vth测量法！(2)Field oxide 上无导电材料覆盖：此结构考虑Acitve range 间implant浓度的Isolation能力，一般是测量Constant current(1uA)下的耐压度 PolyAAFOX25Devi
12、ce Part:10)Capacitance(thickness meas)11)Define:电容的结构常见的有一般介质电 12)容与MOS电容两大类，差别在参13)考极板的组成成分！14)Measurement method:(HP4284)15)(1)For 一般介质电容：16)Force Voltage的极性与电容大小无关！17)(2)for MOS电容：18)Gox电容的测量方面，要避免空乏层19)电容的形成，才能算出Thickness20)Poly on PW:加负压于Poly gate 上,PW21)接地！22)Poly on NW:加正压于Poly gate 上,NW23)接地
13、！26Process Factor influence on WAT ParaGain factor:=COX(W/L)1)Mobility,Id a)GOX/Si interface quality,mobility,current Gain b)Cannel implant Dose,mobility,current Gain2)P1 CD,L,current Gain3)GOX thickness,COX,current Gain4)GAMMA FACTOR 5)NB,COX(GOX thickness较厚),1.=（2qNB)1/2/COX2.=Vt/(2f+Vbs1)1/2-(2f+
14、Vbs2)1/2)28Process Factor influence on WAT ParaSaturation Current:Id=1/2(COXW/L)(Vgs-Vt)21)Vt implant,Isat2)GOX thickness,COX,Isat 3)Effective channel length Leff,Isat a)Poly1 CD(define Leff),Isat b)S/D implant c)Thermal Budget,Isat(Lateral Diffusion)4)Weff,Isat a)Nitride CD,Weff,Isat b)Birds beak encorach,Isat29 Example introduce Case1:P1/P2 Cap.Fail(lower)Case2:P+Rs Fail(higher)Case3:NMOS Idsat Fail(lower)Case4:PMOS Idsat Fail(lower)Case5:N/P MOS Isat all Fail(lower)31simple32