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1、第二章 部分习题答案2.1(d)67.248=110111.0101002(e)10100.11012=14.D16(i)101111.01112=57.348(j)15C.3816=101011100.0011122.2(a)12348=10100111002=29C16(e)7436.118 2=F1E.24162.3(b)7E6A162=771528(e)9E36.7A16 2=117066.36482.5(e)10100.11012=20.812510(j)15C.3816=348.21875102.6(b)348910=66418(f)2385110=5D2B16 补充：125.17
2、10=1111101.001012,2-52.7(a)C 1 1 0 0 1 0 01 1 0 0 1 11 1 0 1 0+1 0 0 1 1 0 12.8(b)B 1 1 1 0 0 0 01 0 0 1 1 11 0 1 0 1 0+1 1 1 1 0 1 2.9(b)C 1 1 1 1 0 5 7 7 3 4 1 0 6 6+6 1 0 2 22.10(c)C 1 0 1 1 0F 3 5 B2 7 E 6+1 1 B 4 1 2.11 8-bit signed-magnitude+258-bit twos 8-bit ones 00011001 00011001 00011001+1
3、20 01111010 01111010 01111010+82 01010010 01010010 01010010-42 10101010 11010110 11010101-6 10000110 11111010 11111001-111 11101111 10010001 100100002.12(b)C 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1+1 0 0 1 1 1 1 0(c)C 1 1 1 0 0 0 1 00 1 0 1 1 1 0 10 0 1 1 0 0 0 1+1 0 0 0 1 1 1 0 no overflo
4、w overflow第3 章 部分习题答案3.1(a)0(b)0(c)1(d)probably 0(e)undefined(f)probably 0(g)1(h)probably 13.2(a)1(b)1(c)0(d)probably 1(e)undefined(f)probably 1(g)0(h)probably 03.16 A CMOS inverting gate has fewer transistors.3.20 table 3-3 VNH=VOHmin-VIHmin=4.4-3.15=1.25V(IOH=-20A)VNH=VOHmin-VIHmin=3.84-3.15=0.69V
5、(IOH=-4mA)VNL=VILmax-VOLmax=1.35-0.1=1.34V(IOL=20A)VNL=VILmax-VOLmax=1.35-0.33=1.02V(IOL=4mA)3.21 According to figure X3.21 VNH=VOHmin-VIHmin=3.5-2.55=0.95V VNL=VILmax-VOLmax=2.35-1.5=0.85V 3.27(d)IOH=i2-i1=VOH/R2-(5-VOH)/R1=3.84/470-(5-3.84)/470=5.7mAVCCi1i2 IOR1R2IOL=i2-i1=VOL/R2-(5-VOL)/R1=0.33/4
6、70-(5-0.33)/470=-9.24mA3.40 The voltage drop of resistor is:VCCRLED+-2VVOLVR=5.0-2-VOL=3-0.33=2.67VThereforeR=2.67V/0.005=5323.49 Table 3-10(a)“Excess”driving capability（剩余驱动能力）is 80A in the HIGH state.3.49 Table 3-10(b)“Excess”driving capability（剩余驱动能力）is 140A in the HIGH state.3.53 According to Ta
7、ble 3-10 VNH=VOHmin-VIHmin=2.7-2.0=0.7V VNL=VILmax-VOLmax=0.8-0.5=0.3V 3.56 Table 3-6,3-7,3-10(b)74LS driving 74HCT VNH=VOHmin-VIHmin=2.7-2.0=0.7V VNL=VILmax-VOLmax=0.8-0.5=0.3V 3.57 Table 3.6,3-7,3-10(a)74HCT driving 74LS“Excess”driving capability（剩余驱动能力）is 3.8mA in the HIGH state.第4 章 部分习题答案4.5 错误
8、在于改变了以前的计算顺序。(WX+YZ)=(W+X)(Y+Z)4.6(a)F=0(b)F=AB+ACE F=ABC+ABC+ABC+ABC4.9(c)F=(A+B+C)(A+B+C)(A+B+C)(A+B+C)F=WXY+WXY+WXY4.9(d)F=(W+X+Y)(W+X+Y)(W+X+Y)(W+X+Y)(W+X+Y)F=XYZ+XYZ+XYZ+XYZ+XYZ4.9(e)F=(X+Y+Z)(X+Y+Z)(X+Y+Z)F=X+YZ4.14(a)ZXY00 01 11 100111 1 1 1F=Z+XY4.14(e)ABCD00 01 11 100001111011111111111F=B+A
9、D+ACD4.15(b)F=XY+XZ+WYZ+WXYZ4.15(c)F=BC+AB+ABCYZWX00 01 11 10000111101111 1111CAB00 01 11 100111114.18(a)F=WXY+WYZ+WXZ+WXY4.18(c)F=BCD+ABC+ABCDYZWX00 01 11 1000011110111dd11ABCD00 01 11 10000111101111d4.19(a)YWX00 01 11 100111 1 1F=WX+WY+XY4.19(c)YZWX00 01 11 10000111101111111 1F=WY+WZ+XYZ+YZ+WXY+WX
10、ZStatic-1 hazardHazard-free circuit:11Static-1 hazardHazard-free circuit:4.19(e)YZWX00 01 11 10000111100F=(W+X+Y)(X+Z)(W+Y+Z)Static-0 hazardHazard-free circuit:00 0 004.59(b)YZWX00 01 11 10000111101111111YZWX00 01 11 100001111011111V=0V=1F=VWY+VXY+XYZ+WXYZ4.61 The name of the circuit comes from its
11、output equationF=2B+2B tINVtINVtINVtOR 3tINV第6 章 部分习题答案 6.9 由表6-2 知，74LS00 的最大tpLH 和最大tpHL 均为15ns，所以图X6-9 的最大传播延迟为90ns。6.10 由表6-2 知，74AHCT00 的最大tpLH 和最大tpHL 均为9.0ns，所以最大传播延迟为54ns。6.131INOUT001OUT=IN 1 0 0 1OUT1OUT2OUT3INOUT1OUT2OUT3OUTtpHLtpHLtpHLtpLH3tpHL+tpLH3tpLH+tpHL6.16 低电平有效输出的译码器要快些 ZYXABCG1G
12、2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF(a)F=(X,Y,Z)(2,4,7)6.20CBAABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF(c)F=(A,B,C,D)(0,2,10,12)(d)=ABCD+ABCD+ABCD+ABCD(e)=(ABC+ABC+ABC+ABC)D(f)=D(A,B,C)(0,1,5,6)6.20DCBAABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF(c)F=(W,X,Y)(0,2,4,5)(d)G=(W,X,Y)(1,2,3,6)6.20DG6.21 可怕错误：某个时刻，可能有两个三态
13、缓冲器处于非悬空状态。消除错误方法：将使能信号EN_L 反相后接到2G_L 上。6.286.296.471 0 0 0 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 0 0 0 1 10 0 0 0 1 0 0 0 0 0 0 1 0 00 0 0 0 0 1 0 0 0 0 0 1 0 10 0 0 0 0 0 1 0 0 0 0 1 1 00 0 0 0 0 0 0 1 0 0 0 1 1 10 0 0 0 0 0 0 0 1 0 1 1 1 00 0 0
14、 0 0 0 0 0 0 1 1 1 1 1I0 I1 I2 I3 I4 I5 I6 I7 I8 I9Y3 Y2 Y1 Y010-to-4 encoder truth table6.476.51低电平输入有效，高电平输出有效。第6 章 补充习题1.设计一个3 位奇数检测器电路，当输入为奇数时，即当 ABC=001、011，101，111 时，电路输出为高电平。分别用74x151 复用器和用74x138 译码器实现。解：1）用74x151 实现F=ABC+ABC+ABC+ABC=A,B,C(1,3,5,7)ENABCD0D1D2D3D4D5D6D7YY74x151CBAF100第6 章 补充习题
15、解：2）用74x138 实现F=A,B,C(1,3,5,7)CBAABCG1G2AG2BY0Y1Y2Y3Y4Y5Y6Y774x138+5VF2.用74x151 实现下面逻辑函数：1)F(A,B,C,D)=AB+CD 解：F=AB(C+C)(D+D)+(A+A)(B+B)CD=ABC+ABC+ABCD+ABCD+ABCD+ABCD=ABC+ABC+ABCD+ABCD+ABCD D7=1,D6=1,D5=D D3=D D1=D D0=D2=D4=0ENABCD0D1D2D3D4D5D6D7YY74x151CBAFD0012.用74x151 实现下面逻辑函数：2)G=(W,X,Y,Z)(0,2,4,
16、5,7)解：G=WXYZ+WXYZ+WXYZ+WXYZ+WXYZ=WXY Z+WXY Z+WXY+WXY ZD0=Z,D1=Z,D2=1,D3=Z D4=D5=D6=D7=0ENABCD0D1D2D3D4D5D6D7YY74x151YXWGZ0013.设计一个组合电路，当M 等于0 时，两个2 位二进制数A=A1A0 和B=B1B0 实现全加；当M 等于1 时，两个2 位二进制数实现全减。要求用两片3-8 译码器74X138 实现，必要时可以用门电路。解：M=0 时，A=A1A0 与B=B1B0 全加；M=1 时，A=A1A0 与B=B1B0 全减；真值表：M A1 A0 B1 B0 S1 S
17、0 C0 0 0 0 0 0 0 00 0 0 0 1 0 1 00 0 0 1 0 1 0 00 0 0 1 1 1 1 00 0 1 0 0 0 1 00 0 1 0 1 1 0 0M A1 A0 B1 B0 S1 S0 C0 0 1 1 0 1 1 00 0 1 1 1 0 0 10 1 0 0 0 1 0 00 1 0 0 1 1 1 00 1 0 1 0 0 0 10 1 0 1 1 0 1 10 1 1 0 0 1 1 00 1 1 0 1 0 0 10 1 1 1 0 0 1 10 1 1 1 1 1 0 11 0 0 0 0 0 0 01 0 0 0 1 1 1 1M A1 A
18、0 B1 B0 S1 S0 C1 0 0 1 0 1 0 11 0 0 1 1 0 1 11 0 1 0 0 0 1 01 0 1 0 1 0 0 01 0 1 1 0 1 1 11 0 1 1 1 1 0 11 1 0 0 0 1 0 01 1 0 0 1 0 1 01 1 0 1 0 0 0 01 1 0 1 1 1 1 11 1 1 0 0 1 1 01 1 1 0 1 1 0 0M A1 A0 B1 B0 S1 S0 C1 1 1 1 0 0 1 01 1 1 1 1 0 0 0S1=M A1A0B1B0(2,3,5,6,8,9,12,15)+M A1A0B1B0(1,2,6,7,8,
19、11,12,13)S0=A1A0B1B0(1,3,4,6,9,11,12,14)C=M A1A0B1B0(7,10,11,13,14,15)+M A1A0B1B0(1,2,3,6,8,11)B0B1A0A1EN_L+5VD0_LD7_LD8_LD15_LY0Y1Y2Y3Y4Y5Y6Y7ABCG1G2AG2BABCG1G2AG2BU1U274X13874X138Y0Y1Y2Y3Y4Y5Y6Y7MS14.用4 位先行进位全加器74x283，将8421BCD 码变为余3 码。BCD 码 余3 码0 0 0 00 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 1A3A2A1A0 Y3Y2Y1Y00 0 1 10 1 0 00 1 0 10 1 1 00 1 1 11 0 0 01 0 0 12 1 0 1 03 1 0 1 14 1 1 0 074x283C0A0B0A1B1A2B2A3B3S0S1S2S3C4756321415121141131090A01A11A20A30Y0Y1Y2Y3