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1、Sequential Logic Circuits I2Sequential Logic CircuitsChapter Outline1.Introduction2.Static Latches and Registers3.Dynamic Latches and Registers4.Pulse Registers5.Pipelining6.Schmitt Trigger7.Summary8.Textbook Reference3Sequential Logic Circuits1.Introduction:Classification of Memory ElementsnFinite-
2、State MachineBlock diagram of a Finite-State Machine,using positive edge-triggered registers4Sequential Logic Circuits1.Introduction:Classification of Memory ElementsFSM Example of ZR36060 JPEG Codec A Circle stands for：A specific state A series of specific operationsZR36060 ImageOther Image5Sequent
3、ial Logic Circuits1.Introduction:Classification of Memory ElementsAccording to the storage mechanismsPositive FeedbackCharged BasedStatic MemoryDynamic Memory State can be preserved as long as the power is turned on Not sensitive to disturbance Slower and more area-consuming Capacitors have to be re
4、freshed periodically to compensate the charge leakage Faster and consuming less area6Sequential Logic Circuits1.Introduction:Classification of Memory ElementsForeground Memory(Embedded Into the Logic)Individual Register,Register File/BankIndividual Latch,Latch File/BankBackground Memory(Large Scale,
5、Higher Density)Embedded ROM,RAM,FlashStand alone ROM,RAM,FlashAccording to the memory location in the systemRegister stores data when clock rises(pos.edge triggered)7Sequential Logic Circuits1.Introduction:Classification of Memory ElementsClassification of Foreground Memory:Latch and RegisterLatch s
6、tores data when clock is low,transparent when clock is highPositive latch8Sequential Logic Circuits1.Introduction:Timing Metrics tsetup=Setup Time:the time data input must be valid before the clock edge thold =Hold Time:the time data input must be stable after the clock edge tclk-q =Worst Case Propa
7、gation Delay:the max time that D input is copied to Q output with reference to the clock edge(usually called Propagation Delay).tcdreg=Best Case Propagation Delay:the min time that D input is copied to the Q output with reference to the clock edge(usually called Contamination Delay).9Sequential Logi
8、c Circuits1.Introduction:Timing MetricsClock period should satisfy:Look into different time points:t1 and t210Sequential Logic Circuits1.Introduction:Timing MetricsOnly observe the time points t1thold of FF2 should satisfy:tcd:Contamination Delay or Minimum Delay=-0.083911Sequential Logic Circuits1.
9、Introduction:Timing Metrics ExampleExpected Clock Period:2.5 ns12Sequential Logic Circuits1.Introduction:Timing Metrics12tCLK-Qtp,combtsetupExpected Clock Periodregister1register2Static Timing Analysis Results.Obtained from Synopsys Astro.Refer to the previous slide.13Sequential Logic Circuits1.Intr
10、oduction:Timing Metrics13 Problem One:Assume the rising edge on“Clk”reaches the clock port of Register One(register in the left)at time t 1,and the same rising edge on“Clk”reaches the clock port of Register Two(register in the right)at time t 2.Solve the following 4 problems(in next foil):14Sequenti
11、al Logic Circuits1.Introduction:Timing Metrics14If d d=t 2 t 1=0,calculate the minimum clock period.If d d=t 2 t 1=1,calculate the minimum clock period.If d d=t 2 t 1=4,calculate the minimum clock period.If clock period is set to be 12,derive the range of d d.Problem One:15Sequential Logic Circuits1
12、.Introduction:Timing Metrics15 Solution:d d =t1-t2=0Blue:7Red:9Black:7Brown：616Sequential Logic Circuits1.Introduction:Timing Metrics16 Solution:d d =t2 t1=1Blue :7 1=6Red :9 1=8Black:7Brown:6Black:7Brown:6Sequential Logic Circuits1.Introduction:Timing Metrics17 Solution:d d=t2 t1=4Blue :7-4=3Red :9
13、-4=5Sequential Logic Circuits1.Introduction:Timing Metrics18 Solution:T=12,d d=t2 t1?Blue t2-t1：7-12=-5Red t2-t1：9-12=-3Black t2-t1：dont careBrown t2-t1：dont careLower BoundTo guarantee the updated input data of Register Two,which comes from Register One,could be established reliably.Sequential Logi
14、c Circuits1.Introduction:Timing Metrics19 Solution:T=12,d d=t2 t1?Blue t2-t1：6Red t2-t1：8Black t2-t1：dont careBrown t2-t1：dont careUpperBoundTo guarantee the old data waiting at the input port of Register Two not to be contaminated by the updated data from Register One.20Sequential Logic CircuitsCha
15、pter Outline1.Introduction2.Static Latches and Registers3.Dynamic Latches and Registers4.Pulse Registers5.Pipelining6.Schmitt Trigger7.Summary8.Textbook ReferenceSequential Logic Circuits2.Static Latches and Registers21Bistable PrincipleMultiplexer-Based LatchesMaster-Slave Edge-Triggered RegisterLo
16、w-Voltage Static LatchesStatic SR Flip-FlopsSequential Logic Circuits2.Static Latches and Registers:Bistable Principle22Vi1ACBVo2Vi1=Vo2Vo1Vi2Vi2=Vo1Two cascaded invertersThree possible operation points:A,B and CTwo stable operation points:A and BVi1Vo2Vo1Vi2Vi2=Vo1Vi1=Vo2 Positive Feedback:Bi-Stabi
17、lityVTC of two cascaded invertersSequential Logic Circuits2.Static Latches and Registers:Bistable Principle23 Metable versus Stable Operation PointsSequential Logic Circuits2.Static Latches and Registers:Bistable Principle24 About Noise Margins Largest squares that fit in the graph are a measure for
18、 the noise margin.Both,diagonal and side of the square are used to quantify Seevinck,JSSC 10/87Sequential Logic Circuits2.Static Latches and Registers:Bistable Principle25 No triggering:bistable circuit remains in one of the stable states and thus remembers a value,this is the memory function Trigge
19、ring can be done in two waysCut the feedback loop multiplexer based latch/registerOverpower the feedback loopSequential Logic Circuits2.Static Latches and Registers:Bistable Principle26Naming ConventionsIn our textbook:A flip-flop is a bistable circuitA latch is a level sensitive flip-flop.A registe
20、r is a edge-triggered flip-flop.There are many different naming conventionsFor instance,many open literatures call edge-triggered elements flip-flops,which leads to confusion however.Sequential Logic Circuits2.Static Latches and Registers271.Bistable Principle2.Multiplexer-Based Latches3.Master-Slav
21、e Edge-Triggered Register4.Low-Voltage Static Latches5.Static SR Flip-FlopsSequential Logic Circuits2.Static Latches and Registers28 Mux based on transmission gate or switch nMOS onlyless load to the clock,But VA limited to VDD-VTNDegraded noise marginStatic power in first invertorSolutions for this
22、 exist!Sequential Logic Circuits2.Static Latches and Registers:Multiplexer-Based Latches29Mux-based Latch Transistor ImplementationSequential Logic Circuits2.Static Latches and Registers301.Bistable Principle2.Multiplexer-Based Latches3.Master-Slave Edge-Triggered Register4.Low-Voltage Static Latche
23、s5.Static SR Flip-FlopsSequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register31Master-Slave Edge-Triggered RegisterPositive edge triggered register is formed by cascadingMaster latch=negative latchSlave latch=positive latchSequential Logic Circuits2.Static Latch
24、es and Registers:Master-Slave Edge-Triggered Register32 Master-Slave edge-triggered register transistor implementation by using transmission gatePositive or Negative Edge-Triggered?Sequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register33 Timing ParameterSetup ti
25、me？3 tpd_inv+tpd_txHold time？0Propagation delay？tpd_inv+tpd_txPositive Edge-TriggeredAssume 0 delay of this inverterSequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register34 Example:t Setup simulation of master-salve edger-triggered registerVoltage(V)Time(ns)Time
26、(ns)tsetup=0.21ns0.21ns0.20nsVoltage(V)FAIL!Sequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register35 Example:t clk-q simulation of master-salve edger-triggered registerSequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register36
27、 Problem Two:It is possible to remove the inverter I1 and I4 without loss of functionality.Is there any advantage to include these inverters?Sequential Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register37 Reduce the clock load of static master-slave register(using “ove
28、rpower the feedback loop”approach rather than multiplexer).Cons:T1 must be stronger than I2.Ratioed logic,more complex.Reverse conduction.It is possible for the combination of T2 and I4 to influence the data stored in the I1-I2 latch.Pros:clock load is reduced from 8 to 4.Sequential Logic Circuits2.
29、Static Latches and Registers:Master-Slave Edge-Triggered Register38 Non-Ideal Clock Signal:Overlapping between CLK and CLKDuring 1-1 overlap,node A is driven from B and D.State of A is undefined.During 1-1 overlap,both latches are transparent.There is a direct path from D to Q(race condition).Sequen
30、tial Logic Circuits2.Static Latches and Registers:Master-Slave Edge-Triggered Register39 Solution:using non overlapping clocksPseudostatic two-phase D registerStorage is dynamic during 0-0 overlap How to generate Nonoverlapping clocks:Problem 7.2,P339 of Textbook.Sequential Logic Circuits2.Static La
31、tches and Registers401.Bistable Principle2.Multiplexer-Based Latches3.Master-Slave Edge-Triggered Register4.Low-Voltage Static Latches5.Static SR Flip-FlopsSequential Logic Circuits2.Static Latches and Registers:Low-Voltage Static Latches41 Low-Voltage Static LatchesNormal mode of OperationuSLEEP=0u
32、When CLK=0,D-QuWhen CLK=1,hold mode,cross-coupled feedback is enabledSleep or Idle modeuSLEEP=1uCLK=1,extra inverter is used to store the stateuSubstantially reduce leakage currentsExtra InverterSequential Logic Circuits2.Static Latches and Registers:Low-Voltage Static Latches42010 Problem Three:One
33、 of the NMOS and PMOS high-threshold devices be eliminated or not?Leakage PathSequential Logic Circuits2.Static Latches and Registers431.Bistable Principle2.Multiplexer-Based Latches3.Master-Slave Edge-Triggered Register4.Low-Voltage Static Latches5.Static SR Flip-FlopsSequential Logic Circuits2.Sta
34、tic Latches and Registers:Static SR Flip-Flop44 NOR-based SR flip-flop(Overpowering the feedback loop)Forbidden State（b）Characteristic table11000100（a）Schematic diagram Forbidden state:u Q is no longer the complement of Qu The resulting state of the latch is unpredictable after the input triggers re
35、turn to their zero levels.Sequential Logic Circuits2.Static Latches and Registers:Static SR Flip-Flop45 Clocked SR Flip-Flop(synchronous sequential circuit)RSQQ01010011Q100Q010Clk1111XXQQ0SRQQSRQQClk（a）Schematic Diagram（b）Characteristic tableLogic symbol of NOR-based SR flip-flopSynchronous design m
36、ethodology is the preferred strategy for more than 99%of todays integrated circuits.Sequential Logic Circuits2.Static Latches and Registers:Static SR Flip-Flop46VDDClkSClkRQQM1M3M4M2M5M6M7M8 Q=1,R pulse is applied：u VQ VM12（Switching threshold of inverter composed of M1 and M2)u Transistor sizes of
37、M4,M7 and M8 deserve to be carefully selectedQ=0,S pulse is appliedu VQ 1 transition on Q only ifL=0.25umSequential Logic Circuits2.Static Latches and Registers:Static SR Flip-Flop48Output voltage versus pull-down device size M5 and 6(W2/L2=1.5um/0.25um)Transient response showing that M5 and M6 must each have a W/L larger than 3 to switch SR flip-flop Example:transistor sizing of clocked SR Latch49Sequential Logic CircuitsChapter Outline1.Introduction2.Static Latches and Registers3.Dynamic Latches and Registers4.Pulse Registers5.Pipelining6.Schmitt Trigger7.Summary8.Textbook Reference