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1、The series SCM of AT89 1.1 AT89C511.Featuresl 4K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cyclesl Three-level Program Memory Lockl 128 x 8-bit Internal RAMl 32 Programmable I/O Linesl Two 16-bit Timer/Countersl Six Interrupt Sourcesl Low-power Idle and Power-down M
2、odes2.DescriptionThe AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 inst
3、ruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and
4、cost-effective.3.Pin Configurations4Pin DescriptionVCCSupply voltage.GNDGround.Figure A1Port 0Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may al
5、so be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are requ
6、ired during program verification.Port 1Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that a
7、re externally being pulled low will source current (TTL) because of the internal pullups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four
8、TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (TTL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from e
9、xternal program memory and during accesses to external data memory that use 16-bit addresses (MOVX DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Special Fun
10、ction Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins th
11、ey are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (TTL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below:Port 3 also receives some co
12、ntrol signals for Flash programming and verification.RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets the devicePSENProgram Store Enable is the read strobe to external program memory. When the AT89C51 is executing code from external program memory, PSE
13、N is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.ALE/PROGAddress Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) duri
14、ng Flash programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by
15、 setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.EA/VPPExternal Access Enable. EA must be strapped to GN
16、D in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-vol
17、t programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier. 5.Oscillator CharacteristicsXTAL1 and XTAL2 are the
18、input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is drive
19、n as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.6.Idle ModeIn idle mode, the CP
20、U puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should
21、 be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
22、is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.7.Power-down ModeIn the power-down mode, the oscillator is stopp
23、ed, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RA
24、M. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.8.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obta
25、in the additional features listed in the table below. 9.Programming the FlashThe AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltag
26、e (VCC) program enable signal. The low-voltage programming mode provides a convenient way to program the AT89C51 inside the users system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltag
27、e or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must
28、 be erased using the Chip Erase Mode. Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figure 3 and Figure 4. To program the AT89C51, take the following steps. （1）Input the desired memory l
29、ocation on the address lines.（2）Input the appropriate data byte on the data lines.（3）Activate the correct combination of control signals.（4）Raise EA/VPP to 12V for the high-voltage programming mode. （5）Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is
30、 self-timed and typically takes no more than 1.5 ms.（6） Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling:The AT89C51 features Data Polling to indiate the end of a write cycle. During a write cycle, an attempted
31、read of the last byte written will result in the complement of the written datum on P0.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte
32、 programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code da
33、ta can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: The entire Flash array is erased electrically by using the proper combination of control
34、signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 0
35、31H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming1.2 AT89C52 The AT89C52 is a low-power, high-
36、performance CMOS 8-bit microcomputer with 8K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 and 80C52 instruction set and pinout The on-chip Flash
37、 allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded
38、control applications.The AT89C52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C52 is de
39、signed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions un
40、til the next hardware reset.Features： Compatible with MCS-51 Products 8K Bytes of In-System Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles Fully Static Operation: 0 Hz to 24 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Cou
41、nters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down ModesPin Description：VCC: Supply voltageGND: GroundAT89 系列单片机1.1 AT89C511、特性n 内含4KB的flash存储器，擦写次数1000次；n 具有可编程的3级程序锁定器；n 内含128字节的RAM；n 具有32根可编程的I/O线；n 具有2个16位可编程定时器；n 具有6个中断源；n 两种低功耗工作模式，即空闲模式和掉电模式； 2、概述AT89C51是一
42、种低功耗，高性能，采用CMOS工艺的8KB的可在线编程的Flash存储器。该单片机采用了ATMEL公司的高密度、非易失性存储器技术，与工业标准型MCS-51单片机的指令系统和引脚完全兼容；片内的Flash存储器可在线重新编程，或使用通用的非易失性存储器编程器；通用的8位CPU与在线可编程Flash集成在一块芯片上，从而使AT89C51功能更加完善，应用更加灵活；具有较高的性能价格比.3、AT89C51单片机的封装形式4、引脚描述VCC电源电压输入引脚。GND电源地。P0口8位、开漏极、双向I/O口。P0口可用作通用I/O口，但须外接上拉电阻，每个引脚可吸收8个TTL灌电流，当作为输入时，首先应
43、将引脚置1。P0口也可用作访问外部程序存储器和数据存储器时的低8位地址/数据总线的复用线。在该模式下，P0口含有内部上拉电阻。在Flash编程时，P0口接收代码字节数据；在编程校验时，P0口输出代码字节数据。P1口8位、双向I/O口，内部含有上拉电阻。P1口可作普通I/O口。输出缓冲器可驱动4个TTL负载；用作输入时，先将引脚置1，由片内上拉电阻将其抬到高电平。P1口的引脚可由外部负载拉到低电平，通过上拉电阻提供拉电流。在Flash并行编程和校验时，P1口可输入地字节地址。P2口具有内部上拉电阻的8位双向I/O口。P2口用作输出口时，可驱动4个TTL负载；用做输入口时，先将引脚置1，由内部上拉
44、电阻将其提高到高电平。若负载为低电平，则通过内部上拉电阻向外输出电流。CPU访问外部16位地址的存储器时，在Flash并行编程和校验时，P2口可输入高字节地址和某些控制信号。在P3口具有内部上拉电阻的8位双向口。P3口用做输出口时，输出缓冲器可吸收4个TTL的灌电流；用做输入口时，首先将引脚置1，由内部上拉电阻抬为高电平。若外部的负载是低电平，则通过内部上拉电阻向外输出电流。在与Flash并行编程和校验时，P3口可输入某些控制信号。P3口除了通用I/O功能外，还有替代功能。RST复位输入信号，高电平有效。在振荡器稳定工作时，在RST脚施加两个机器周期（即24个晶振周期）以上的高电平，将器件复位
45、。片外程序存储器读选通信号PSEN（Program Store Enable）,低电平有效。当AT89C51执行来自外部程序存储器的指令代码时，每个机器周期两次有效。在访问外部数据存储器时，无效。ALE/低字节地址锁存信号ALE（Address Latch Enable）。在系统扩展时，ALE的下降沿将P0口输出的低8位地址琐存在外接的地址琐存器中，以实现低字节地址和数据的分时传送。此外，ALE端连续输出正脉冲，频率为晶振频率的1/6，可用做外部定时脉冲使用。但要注意，每次访问外RAM时要丢失一个ALE脉冲。再编程期间，该引脚输入编程脉冲（）。如果需要，则通过SFR（8EH）的第0位置1，可禁
46、止ALE操作，但在使用MOVC或MOVX指令时，ALE仍然有效。也就是说，ALE的禁止位不影响对外部存储器的访问。/Vpp外部程序存储器访问允许信号EA（External Access Enable）。当信号接地时，CPU只执行片外程序存储器中的程序；当接Vcc时，CPU首先执行片内程序存储器中的程序（0000H-0FFFH），然后自动转向执行片外程序存储器中的程序（1000H-FFFFH）。如果程序锁定位LB1被编程，那么值将在复位时由片内锁存。在与Flash并行编程时，该引脚可接入12V的编程电压Vpp。XTAL1是片内振荡器反相放大器和时钟发生器的输入端。XTAL2是片内振荡器反相放大器
47、的输出端。5、振荡器的特性当使用片内振荡器时，片外振荡源和电容与XTAL1和XTAL2的接法如图B3所示。可以使用晶体谐振器和陶瓷谐振器。当使用外部振荡器信号时，外部时钟信号接入XTAL1引脚，XTAL2引脚悬空。对外部时钟信号的占空比没有要求，但高低电平持续时间不应过短。6、空闲模式在空闲模式下，CPU处于睡眠状态，振荡器和所有片内外围电路仍然有效。空闲模式可由软件设置进入。在这种模式下，片内RAM和SFR中的内容保持不变。空闲模式可通过任何一个允许中断或硬件复位退出。若用硬件复位方式结束空闲模式，则在片内复位控制逻辑发生作用前长达约两个机器周期时间内，器件从断点处开始执行程序。片内硬件禁止
48、访问内部RAM，但不禁止访问端口。为避免采用复位方式退出空闲模式时对端口的不应有的访问，在紧随设置进入空闲指令的后面，不能是写端口或外部RAM的指令。7、掉电模式在掉电模式下，振荡器停止工作，CPU和片内所有外围部件均停止工作，但片内RAM和SFR中的内容保留不变，直到掉电模式结束。复位可重新设置SFR中的内容，但不改变片内RAM中的内容。在Vcc电源恢复到正常值并维持足够长的时间之后，允许振荡器恢复并达到稳定，方可进行复位，以退出掉电模式。8、程序存储器锁定位AT89C51内含3个程序锁定位，可维持原来的非编程状态（U），或对其进行编程（P），从而得到不同的保护性能。9、Flash存储器的编程方式AT89C51是在芯片擦除的状态下准备编程的，编程接口接受高电压或低电压编程信号。低电压编程为用户系统提供了一个方便的编程方式，而高电压编程与一般常用的EPROM编程器兼容。AT89C51有低电压和高电压编程两种模式，其顶端标志和型号。AT89C51存储器在编程状态下都是一个字节编程，Flash中各个单元是非空的，应先将芯片擦除后，方可进行编程。其编程算法是在编程之前，必须将地址、数据、控制信号按表B5和图B5和B6设置，变成可按下列步骤：（1） 在地址线上输入存储单元地址；（2） 在数据线上输入对应数据；（3） 组合正确的控制信号；（4） 对于高电压编程模式