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1、 机电设计工程师岗位职责 机电设计工程师 Mechatronics Desing Engineer 粉瑞得制药设备(上海)有限公司 粉瑞得制药设备(上海)有限公司,粉瑞得 职责描述: Job Description: 1. Responsible for mechanical and electrical design of company products, complying with GMP, FDA etc for pharma, chemical and food industry; 根据GMP、FDA等制药/化工/食品等行业要求,进展公司产品的机械与电气设计; 2. Design
2、for 3D model, PLC and touch screen, select for spare parts, electrical components, complete mechanical drawing, wiring diagram and BOM; 负责3D模型设计、PLC程序及触摸屏设计,零部件和电气元器件选型、出具工程图纸、电器接线图及零部件和元器件明细表等; 3. Provide technical proposal to support company business, check URS and give tech solution 帮助业务部门为工程供应技术
3、方案和支持, 审核URS并依据客户需求供应解决方案; 4. Design for outsource processed components, and guide suppliers to improve quality requirement; 供给商外协构件设计、指导供给商提高质量要求; 5. Participate in improvement of product quality, optimize the assembly procedure and process 参加产品质量整改、产品装配和工艺流程优化; 6. Participate in technical seminar
4、and product promotion; 参加技术研讨与产品技术推广等活动; 7. Support for lab test and relevant tasks; 帮助工艺部门完成试验及相关工作; 8. Responsible partly for FAT/SAT as required; 依据公司需要负责局部验收测试(FAT/SAT); 9. Timely fulfill other duties as assigned by the Superior. 精彩完成上级领导指派的其他工作任务。 任职要求: Job Requirements -大学专科及以上学历,机电一体化专业毕业; -具
5、有一年以上机械及电气设计工作阅历; -娴熟操作Solidworks 或AutoCAD制图软件或其他3D软件; -把握机械设备的电器原理图、电器接线图 -熟识西门子PLC200及触摸屏,变频器等应用技术; -能够进展常用机械传动零部件、气动元器件、电器元器件的选型; -了解机械加工工艺、焊接工艺、钣金制作工艺等根本技术; -了解不锈钢制作工艺者优先; -英语根底良好,能读懂英文技术资料。 篇2:数字后端设计工程师岗位职责 数字后端设计工程师 西安紫光国芯半导体有限公司 西安紫光国芯半导体有限公司,华芯半导体,西安紫光国芯,西安紫光国芯半导体有限公司,紫光国芯 ASIC Backend Desig
6、n Engineer (BE) 数字后端设计工程师 Responsibilities: 1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route. 2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analys
7、is. 3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS). 4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization. 5. Static Timing analysis (Prime Time) and setup/hold fix. 6. Formal Verification for equi
8、valence checking (Formality). 7. Generation of fill structures according to technology requirements. Requirements: 1. 4 years experience in backend design flow (APR) with proven SOC tape-out experience. 2. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Comp
9、iler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus. 3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus. 4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus. 5. Good analytical and debugging skills. 6. Good command of English.