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1、文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.基于 51 单片机的电子数字钟设计的外文翻译 AT89C51 Family Users Guide 1 Features Compatible with MCS-51 Products 4K Bytes of In-System Reprogrammable Flash Memory Endurance 1000 WriteErase Cycles Fully Static Operation 0 Hz to 24 MHz Three-level Program Memory Lock 128 x 8-bit Internal R
2、AM 32 Programmable IO Lines Two 16-bit TimerCounters Six Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes 2 Description The AT89C51 is a low-power high-performance CMOS 8-bit microcomputer with 4K bytes of Flash programmable and erasable read only memory PEROM The de
3、vice is manufactured using Atmels high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set and pin-out The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer By combining a vers
4、atile 8-bit CPU with Flash on a monolithic 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.chip the Atmel AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective solution to many embedded control applications 3 Pin Configurations 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.4 Lock Diagram The AT8
5、9C51 provides the following standard features 4K bytes of Flash 128 bytes of RAM 32 IO lines two 16-bit timercounters a five vector two-level interrupt architecture a full duplex serial port on-chip oscillator and clock circuitry In addition the AT89C51 is designed with static logic for operation do
6、wn to zero frequency and supports two software selectable power saving modes The Idle Mode stops the CPU while allowing the RAM timercounters serial port and interrupt system to continue functioning The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functi
7、ons until the next hardware reset 5 Pin Description VCC Supply voltage GND Ground Port 0 Port 0 is an 8-bit open-drain bi-directional IO port As an output port each pin can sink eight TTL inputs When 1s are written to port 0 pins the pins can be used as high-impedance inputs Port 0 may also be confi
8、gured to be the multiplexed low-order addressdata bus during accesses to external program and data memory In this mode P0 has internal pull-ups Port 0 also receives the code bytes during Flash programming and 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.outputs the code bytes during program verification External
9、 pull-ups are required during program verification Port 1 Port 1 is an 8-bit bi-directional IO port with internal pull-ups The Port 1 output buffers can sinksource four TTL inputs When 1s are written to Port 1 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Por
10、t 1 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 1 also receives the low-order address bytes during Flash programming and verification Port 2 Port 2 is an 8-bit bi-directional IO port with internal pull-ups The Port 2 output buffers can sink
11、source four TTL inputs When 1s are written to Port 2 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 2 pins that are externally being pulled low will source current IIL because of the internal pull-ups Port 2 emits the high-order address byte during fetche
12、s from external program memory and during accesses to external data memory that uses 16-bit addresses MOVX DPTR In this application it uses strong internal pull-ups when emitting 1s During accesses to external data memory that uses 8-bit addresses MOVX RI Port 2 emits the contents of the P2 Special
13、Function Register Port 2 also receives the high-order address bits and some control 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.signals during Flash programming and verification Port 3 Port 3 is an 8-bit bi-directional IO port with internal pull-ups The Port 3 output buffers can sinksource four TTL inputs When
14、1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs As inputs Port 3 pins that are externally being pulled low will source current IIL because of the pull-ups Port 3 also serves the functions of various special features of the AT89C51 as listed below
15、 Port Pin Alternate Functions P30 RXD serial input port P31 TXD serial output port P32 INT0 external interrupt 0 P33 INT1 external interrupt 1 P34 T0 timer 0 external input P35 T1 timer 1 external input P36 WR external data memory write strobe P37 RD external data memory read strobe Port 3 also rece
16、ives some control signals for Flash programming and verification RST Reset input A high on this pin for two machine cycles while the oscillator is running resets the device ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory This pin is a
17、lso the program pulse input PROG during Flash programming In normal operation ALE is emitted at a constant rate of 16 the oscillator frequency and may be used 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.for external timing or clocking purposes Note however that one ALE pulse is skipped during each access to ext
18、ernal Data Memory If desired ALE operation can be disabled by setting bit 0 of SFR location 8EH With the bit set ALE is active only during a MOVX or MOVC instruction Otherwise the pin is weakly pulled high Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode
19、 Program Store Enable is the read strobe to external program memory When the AT89C51 is executing code from external program memory is activated twice each machine cycle except that two activations are skipped during each access to external data memory VPP External Access Enable must be strapped to
20、GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH Note however that if lock bit 1 is programmed will be internally latched on reset should be strapped to VC C for internal program executions This pin also receives the 12-volt program
21、ming enable voltage VPP during Flash programming for parts that require 12-volt VPP XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit XTAL2 Output from the inverting oscillator amplifier 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.6 Oscillator Characteristics XT
22、AL1 and XTAL2 are the input and output respectively of an inverting amplifier which can be configured for use as an on-chip oscillator as shown in Figure 1 Either a quartz crystal or ceramic resonator may be used To drive the device from an external clock source XTAL2 should be left unconnected whil
23、e XTAL1 is driven as shown in Figure 2 There are no requirements on the duty cycle of the external clock signal since the input to the internal clocking circuitry is through a divide-by-two flip-flop but minimum and imum voltage high and low time specifications must be observed Oscillator Connection
24、s Note C1 C2 30 pF10 pF for Crystals40 pF10 pF for Ceramic ResonatorsExternal Clock Drive Configuration 7 Idle Mode In idle mode the CPU puts itself to sleep while all the on-chip peripherals remain active The mode is invoked by software The content of the on-chip RAM and all the special functions r
25、egisters remain unchanged during this mode The idle mode can be terminated by any enabled interrupt or by a hardware reset It should be noted that when idle is terminated by a hard ware reset the device normally resumes program execution from where it left off up to two machine cycles before the int
26、ernal reset 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.algorithm takes control On-chip hardware inhibits access to internal RAM in this event but access to the port pins is not inhibited To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset the instruction following
27、 the one that invokes Idle should not be one that writes to a port pin or to external memory 8 Power-down Mode In the power-down mode the oscillator is stopped and the instruction that invokes power-down is the last instruction executed The on-chip RAM and Special Function Registers retain their val
28、ues until the power-down mode is terminated The only exit from power-down is a hardware reset Reset redefines the SFRs but does not change the on-chip RAM The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillato
29、r to restart and stabilize 9 Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state that is contents FFH and ready to be programmed The programming interface accepts either a high-voltage 12-volt or a low-voltage VCC program enable signal The lo
30、w-voltage programming mode provides a convenient way to program the AT89C51 inside the users system while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers The AT89C51 is shipped with either 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.the high-voltage or lo
31、w-voltage programming mode enabled The respective top-side marking and device signature codes are listed in the following table The AT89C51 code memory array is programmed byte-by-byte in either programming mode To program any nonblank byte in the on-chip Flash Memory the entire memory must be erase
32、d using the Chip Erase Mode 10 Flash Programming and Verification Characteristics TA 0 C to 70 C VCC 50 10 Note 1 Only used in 12-volt programming mode 11 DC Characteristics TA -40C to 85 C VCC 50V20 unless otherwise noted Notes 1 under steady state non-transient conditions IOL must be externally li
33、mited as follows imum IOL per port pin 10 mA imum IOL per 8-bit port Port 0 26 mA Ports 1 2 3 15 mA imum total IOL for all output pins 71 mA If IOL exceeds the test condition VOL may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 2Min
34、imum VCC for Power-down is 2V 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.12 External Program and Data Memory Characteristics 13 External Program Memory Read Cycle 14 External Data Memory Read Cycle 15 External Data Memory Write Cycle 16 External Clock Drive Waveforms 17 External Clock Drive 18 Serial Port Timi
35、ng Shift Register Mode Test Conditions VCC 50 V 20 Load Capacitance 80 pF 19 Shift Register Mode Timing Waveforms 20 Ring Information 21 Packaging Information AT89C51 系列用户指南1 主要性能参数 MCS-51 产品指令系统完全兼容k 字节可重擦写 Flash 闪速存储器1000次擦写全静态操作0Hz24MHz 三级加密程序存储器1288 字节内部 RAM 32 个可编程 I O 口线2 个 16 位定时计数器6 个中断源程串行
36、UART 通道2 功能特性概述AT89C51 是美国 ATMEL 公司生产的低电压高性能 CMOS8 位单片机片内含 4k bytes 的可反复擦写的只读程序存储器PEROM 和 128 bytes 文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.的随机存取数据存储器RAM 器件采用 ATMEL 公司的高密度非易失性存储技术生产兼容标准 MCS-51 指令系统片内置通用 8 位中央处理器CPU和 Flash 存储单元功能强大 AT89C51 单片机可为您提供许多高性价比的应用场合可灵活应用于各种控制领域文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.4 方框图A
37、T89C51 提供以下标准功能4k 字节 Flash 闪速存储器128 字节内部RAM32个 I O 口线两个 16 位定时计数器一个 5 向量两级中断结构一个全双工串行通信口片内振荡器及时钟电路同时AT89C51 可降至 0Hz 的静态逻辑操作并支持两种软件可选的节电工作模式空闲方式停止 CPU 的工作但允许 RAM定时计数器串行通信口及中断系统继续工作掉电方式保存 RAM 中的内容但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位引脚功能说明Vcc电源电压 GND 地P0 口 P0 口是一组 8 位漏极开路型双向 I O 口也即地址数据总线复用口作为输出口用时每位能吸收电流的方式驱动
38、 8个 TTL 逻辑门电路对端口写 1 可作为高阻抗输入端用在访问外部数据存储器或程序存储器时这组口线分时转换地址低 8 位和数据总线复用在访问期间激活内部上拉电阻在Flash 编程时 P0 口接收指令字节而在程序校验时输出指令字节校验时要求外接上拉电阻P1 口 P1 是一个带内部上拉电阻的 8 位双向 I O 口 P1 的输出缓冲级可驱动吸收或输出电流4 个 TTL 逻辑门电路对端口写1 通过内部的上拉电阻把端口拉到高电平此时可作输入口作输入口使用时因为内部存在上拉电阻某个引脚被外部信号拉低时会输出一个电流IILFlash编程和程序校验期间P1 接收低 8 位地址P2 口 P2 是一个带有内
39、部上拉电阻的 8 位双向 I O 口 P2 的输出缓冲级可驱动吸收或输出电流4 个 TTL 逻辑门电路对端口写1 通过内部的上拉电阻把端口拉到高电平此时可作输入口作输入口使用时因为内部存在上拉电阻某个引脚被外部信号拉低时会输出一个电流IIL在访问外部程序存储器或 16 位地址文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.的外部数据存储器例如执行 MOVXDPTR 指令时 P2 口送出高 8 位地址数据在访问 8 位地址的外部数据存储器如执行 MOVXRI 指令时 P2 口线上的内容也即特殊功能寄存器SFR区中 R2 寄存器的内容在整个访问期间不改变Flash 编程或校验时 P
40、2 亦接收高位地址和其它控制信号P3 口 P3 口是一组带有内部上拉电阻的 8 位双向 I O 口 P3 口输出缓冲级可驱动吸收或输出电流4个 TTL逻辑门电路对 P3 口写入 1时它们被内部上拉电阻拉高并可作为输入端口作输入端时被外部拉低的 P3 口将用上拉电阻输出电流 IILP3 口除了作为一般的 I O 口线外更重要的用途是它的第二功能如下表所示端口引脚第二功能RXD串行输入口 TXD串行输出口外中断 0 外中断 1T0定时计数器 0 外部输入 T1定时计数器 1 外部输入外部数据存储器写选通外部数据存储器读选通P3 口还接收一些用于 Flash 闪速存储器编程和程序校验的控制信号RST
41、复位输入当振荡器工作时RST 引脚出现两个机器周期以上高电平将使单片机复位ALE 当访问外部程序存储器或数据存储器时ALE地址锁存允许输出脉冲用于锁存地址的低8 位字节即使不访问外部存储器ALE 仍以时钟振荡频率的 l 6 输出固定的正脉冲信号因此它可对外输出时钟或用于定时目的要注意的是每当访问外部数据存储器时将跳过一个 ALE 脉冲对 Flash 存储器编程期间该引脚还用于输入编程脉冲PROG 如有必要可通过对特殊功能寄存器 SFR 区中的 8EH 单元的 DO 位置位可禁止 ALE 操作该位置位后只有一条MOVX 和 MOVC 指令 ALE 才会被激活此外该引脚会被微弱拉高单片机执行外部程
42、序时应设置 ALE 无效程序储存允许PSEN输出是外部程序存储器的读选通信号当 AT89C51 由外部程序存储器取指令或数据时每个机器周期两次有效即输出两个脉冲在此期间当访问外部数据存储器这两次有效的信号不出现VPP外部文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.访问允许欲使 CPU 仅访问外部程序存储器地址为 0000HFFFFH 端必须保持低电平接地需注意的是如果加密位 LB1 被编程复位时内部会锁存端状态如端为高电平接 VCC 端 CPU 则执行内部程序存储器中的指令Flash 存储器编程时该引脚加上12V 的编程允许电源 Vpp 当然这必须是该器件是使用 12V 编
43、程电压VppXTAL1振荡器反相放大器的及内部时钟发生器的输入端XTAL2振荡器反相放大器的输出端时钟振荡器AT89C5l 中有一个用于构成内部振荡器的高增益反相放大器引脚 XTAL1 和 XTAL2 分别是该放大器的输入端和输出端这个放大器与作为反馈元件的片外石英晶体或陶瓷谐振器一起构成自激振荡器接石英晶体或陶瓷谐振器及电容 C1C2 接在放大器的反馈回路中构成并联振荡电路对外接电容 C1C2 虽然没有十分严格的要求但电容容量的大小会轻微影响振荡频率的高低振荡器工作的稳定性起振的难易程序及温度稳定性如果使用石英晶体我们推荐电容使用 30pF10pF 而如使用陶瓷谐振器建议选择 40pF10F
44、 用户也可以采用外部时钟采用外部时钟的电路如图 5 右图所示这种情况下外部时钟脉冲接到 XTAL1 端即内部时钟发生器的输入端XTAL2 则悬空内部振荡电路石英晶体时C1C2 30pF10pF陶瓷滤波器 C1C2 40pF10pF外部时钟驱动电路7 空闲节电模式AT89C51有两种可用软件编程的省电模式它们是空闲模式和掉电工作模式这两种方式是控制专 用寄存 器 PCON即 电源控制 寄存器中的PDPCON1 和IDLPCON0 位来实现的 PD 是掉电模式当 PD 1 时激活掉电工作模式单片机进入掉电工作状态 IDL 是空闲等待方式当 IDL 1激活空闲工作模式单片机进入睡眠状态如需同时进入两
45、种工作模式即 PD 和 IDL 同时为 1则先激活掉电模式在空文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.闲工作模式状态CPU 保持睡眠状态而所有片内的外设仍保持激活状态这种方式由软件产生此时片内 RAM和所有特殊功能寄存器的内容保持不变空闲模式可由任何允许的中断请求或硬件复位终止终止空闲工作模式的方法有两种其一是任何一条被允许中断的事件被激活IDLPCON0 被硬件清除即刻终止空闲工作模式程序会首先响应中断进入中断服务程序执行完中断服务程序并紧随RETI中断返回指令后下一条要执行的指令就是使单片机进入空闲模式那条指令后面的一条指令其二是通过硬件复位也可将空闲工作模式终止需
46、要注意的是当由硬件复位来终止空闲工作模式时CPU通常是从激活空闲模式那条指令的下一条指令开始继续执行程序的要完成内部复位操作硬件复位脉冲要保持两个机器周期24 个时钟周期有效在这种情况下内部禁止 CPU 访问片内 RAM 而允许访问其它端口为了避免可能对端口产生意外写入激活空闲模式的那条指令后一条指令不应是一条对端口或外部存储器的写入指令在掉电模式下振荡器停止工作进入掉电模式的指令是最后一条被执行的指令片内 RAM 和特殊功能寄存器的内容在终止掉电模式前被冻结退出掉电模式的唯一方法是硬件复位复位后将重新定义全部特殊功能寄存器但不改变 RAM 中的内容在 Vcc 恢复到正常工作电平前复位应无效且
47、必须保持一定时间以使振荡器重启动并稳定工作Flash 闪 速存 储器 的编 程 AT89C51 单 片 机 内部 有4k 字 节 的Flash PEROM 这个 Flash 存储阵列出厂时已处于擦除状态即所有存储单元的内容均为FFH用户随时可对其进行编程编程接口可接收高电压12V或低电压 Vcc 的允许编程信号低电压编程模式适合于用户在线编程系统而高电压编程模式可与通用EPROM 编程器兼容AT89C51 单片机中有些属于低电压编程方式而有些则是高电压编程方式用户可从芯片上的型号和读取芯片内的名字节获得该信息见下表文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.VPP 12v
48、VPP 5V 芯片顶面标识 AT89C51 xxxx yyww AT89C51 xxxx-5 yyww 签名字节 030H 1EH 030H 51H 032H FFH030H 1EH 030H 51H 032H 05HAT89C51 的程序存储器阵列是采用字节写入方式编程的每次写入一个字节要对整个芯片内的 PEROM 程序存储器写入一个非空字节必须使用片擦除的方式将整个存储器的内容清除Flash 编程和校验特性TA 0 C to 70 C VCC 50 10 注仅用于 12V 编程模式TA -40 C to 85 C VCC 50V 20 unless otherwise noted 注 1 在稳定状态无输出条件下IOL 有以下限制每一引脚最大 IOL10mA 每一 8 位端口 P0 口 26mAP1P2 和 P315mA 全部输出引脚最大 IOL71mA 2掉电模式的最小 Vcc 为 2V 13 外部程序存储器读周期14 外部数据存储器读周期15 外部数据存储器写周期16 外部时钟驱动波形文档来源为:从网络收集整理.word 版本可编辑.欢迎下载支持.17 外部时钟驱动特性串行口时序移位寄存器测试条件Vcc 50V20 负载容抗 80pF 18 移位寄存器时序波形19 产品信息20 封装形式21 封装资料