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1、原文：This design take at MCS-51 monolithic integrated circuit as the core full use hardware source designs one kind of frequency meter,this frequency meter will be measured first that signal enlargement reshaping processing,turns satisfies TTL/which the monolithic integrated circuit I/O mouth accepts
2、the CMOS compatible signal from monolithic integrated circuits T1 input port input direct summation pulse number,the monolithic integrated circuit interior timer fixed time is 1S,by now accumulated the pulse number namely for is measured the signal the frequency.Finally passes through monolithic int
3、egrated circuit processing to deliver to the lcd liquid crystal display monitor demonstration.Central Processing Unit Designs The CPU is the key component of a digital computer.Its purpose is to decode instruction received from memory and perform transfers,arithmetic,logic,and control operations wit
4、h data stored in internal registers,memory,or I/O interface units.Externally,the CPU provides one or more buses for transferring instructions,data,and control information to and from components connected to it.In the generic computer at the beginning of chapter 1,the CPU is a part of the processor a
5、nd is heavily shaded.CPUs,however,may also appear in computers.Small,relatively simple computers called microcontrollers are used in computers and in other digital systems to perform limited or specialized tasks.For example,a microcontroller is present in the keyboard and in the monitor in the gener
6、ic computer;thus,these components are also shaded.In such microcontrollers,the CPU may be quite different from those discussed in this chapter.The word lengths may be short(say,four or eight bits),the number of registers small,and the instruction sets limited.Performance,relatively speaking,is poor,
7、but adequate for the task.Most important,the cost of these microcontrollers is very low,making their use cost effective.In the following pages,we consider two computer CPUs,one for a complex instruction set computer(CISC)and the other for a reduced instruction set computer(RISC).After a detailed exa
8、mination of the designs,we compare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance.Finally,we relate the design ideas discussed to general digital system design.1、The complex instruction set computer The first design we present is for a c
9、omplex instruction set computer with a non-pipelined datapath and microprogrammed control unit.We begin by describing the instruction set architecture,including the CPU register set,instruction formats,and addressing modes.The word 文档 可自由复制编辑 CISC nature of the instruction set architecture is demons
10、trated by its memory-to-memory access for data manipulation instructions,eight addressing modes,two instruction format lengths,and instructions that require significant sequences of operations for their execution.We design a datapath for implementing the CISC architecture.The datapath is based on th
11、e one initially described in Section 7-9 and incorporated into a CPU in section 8-10.modifications are made to the register file,the function unit,and the buses to support the present instruction set architecture.Once the datapath has been specified,a control unit is designed to complete the impleme
12、ntation of the instruction set architecture.The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization.In particular,dividing the microprogram into microroutines,while at the same time designing the sequencer with which th
13、ey interact,is a key part of the design.Even the instruction fields and opposed are tied to this coordinated effort.Following the definition of the hardware and microcode organizations,we detail essential parts of the microcode and the microroutines for representative operations.Instruction set arch
14、itecture Figure 10-1 shows the CISC register set accessible to the programmer.All registers have 16 bits.The register file has eight registers,R0 though R7.R0 is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destinatio
15、n.In additional to the register file,there is a program counter PC and stack pointer SP.The presence of a stack pointer indicates that a memory stack is a part of the architecture.the final register is the processor status register PSR,which contains information only in its rightmost the five bits;t
16、he remainder of the register is assumed to contain zero.The PSR contains the word 文档 可自由复制编辑 four stored status bit values Z,N,C,and V in positions 3 through 0,respectively.In additional,a stored interrupt enable bit EI appears in position 4.Table 10-1 contains the 42 operations performed by the ins
17、tructions.Each operation has a mnemonic and a carefully selected oppose.The operations are divided into four groups based on the number of explicit operands and whether the operation is branch.In addition,the status bits affected by the operation are listed.Figure 10-2 gives the instruction formats
18、for the CPU.The generic instruction format has five fields.The first,OPCODE,specifies of the operation.The next two,MODE and S,are used to determine the addresses of the operands.The last two fields,SRC and DST,are the 3-bit source register and destination register address fields,respectively.In add
19、ition,there is an optional second word W that appears with some instructions as an operand or an address,but not with others.The first two bits of OPCODE,IR(15:14),determine the number of explicit operands and how the fields of the format are used.When these bits are 00,either no operand is required
20、 or the location of the operand is implied by OPCODE.Only the OPCODE field is needed,as shown in figure 2(b).the four rightmost OPCODE bits can specify up to 16 operands or with implied operand addresses.If IR(15:14)is 01,the instruction has one operand and is a data transfer or data manipulation in
21、struction.Since there is an operand,the MODE field specifies the addressing mode for obtaining it.The single address may involve the DST register address in its formation,so the DST field is also present.The S field and SRC field relate to the presence of two operands and so are not used for the typ
22、ical single operand instructions.but,the shift instructions require a shift amount to indicate how many bits to shift.For maximum flexibility,word 文档 可自由复制编辑 this shift amount is treated just like a source operand.As a consequence,the SHA and S fields is a full 16-bit operand,but only values 0 throu
23、gh 15 are meaningful.There are sufficient OPCODE bits for 16 instructions with a single operand.Table 10-2 gives the addressing modes specified by the MODE field.The first two bits of MODE specify four different types of addressing:register,immediate,indexed,and relative to the PC.The third bit of M
24、ODE specifies whether the address generated by these modes is used as an indirect address.The one exception to this is direct addressing,which is obtained by applying indirection to the immediate type.Otherwise,if the third bit equals 0,indirect addressing does not apply whereas,if it equals 1,indir
25、ect addressing does apply.For the register type of instruction,MONE(2:1)=00 and the W word is not needed.Since the operand or address comes from a register.The third column of the table provides register transfer statements for each of the addressing modes for the one-operand instructions.If IR(15:1
26、4)is equal to 10,then the instruction has two addresses used for true operands.All fields of the generic instruction,including S and SRC,are used for this case for all instructions.one of addresses,either the source or the destination,uses the addressing modes.If S=0,then the source uses the address
27、ing mode specified by MODE,and the source is a register.If S=1,then the destination uses the addressing mode,and the source is a register.Register transfer descriptions of the resulting addresses are given in the fourth and fifth columns of Table 2.Again,depending on the contents of the MODE field,t
28、he second instruction word W,which is an address or an immediate operand,may or may not be present.Instructions with IR(15:14)=11 are branches.Aside form the S field and the SHA field for shifts,the format is the same as for IR(15:14)=01.For all instructions of this type,the destination address(not
29、the operand)becomes the new address placed in the program counter PC.As a consequence,the register mode is invalid for branch instructions.Before proceeding to the next step,which defines the datapath to support the instruction set architecture,we will briefly note the characteristics of the archite
30、cture that define it as CISC or RISC.Most of the operations given in Chapter 9 are included in the instruction set.A number of operations that do not appear are redundant.The same actions can be achieved by using proper addressing modes with instructions that do appear.For example,LD,ST,IN,and OUT c
31、an all be achieved by using MOVE instructions in a memory-mapped structure.By looking at the formats for the instructions,we find that most of the instructions can operate directly on operate directly on operands from memory.There are eight addressing modes and two different lengths of instruction f
32、ormats.In addition,some of the instructions perform complex operations which can be viewed as operations that are likely to take more than one clock cycle for the execution step.These characteristics clearly identify this as a CISC architecture.word 文档 可自由复制编辑 Datapath organization Rather than begin
33、ning from scratch,we will reuse the non-pipelined datapath employed with the microprogrammed control in section 8-10,with modifications.That datapath was shown in section 8-10,and the new,modified datapath based on it is given in Figure 10-6.we treat each modification in turn,beginning with the regi
34、ster file.In section 8-10,register R8 was used as a temporary storage location.In the new microprogrammed architecture,there are complex instructions spanning many clock cycles and performing complicated operations.Thus,more temporary storage is needed for use by the microprograms.To meet this need,
35、we expand the register file from 9 registers to 16.the first 8 registers,R0 through R7,are visible to the computer programmer.The second 8 registers,R8 though R15,are used as temporary storage for the microprogram operands and are hidden from the programmer.Figure 10-3 provides a map of the expanded
36、 register file with the temporary registers shaded.As indicated previously,register R0 supplies the constant 0.registers R1 through R7 are available to the programmer for use,and registers R8 through R15 provide general temporary storage for use by microprograms,the last four registers,R12 though R1
37、5,have special uses:to keep the microcode simple,standard locations are essential for storing the operands and addresses used by execution microcode for most instructions.thus,R12 is the location for the source address(SA),R13 for the source data(SD),R14 for the destination address(DA),and R15 for t
38、he destination data(DD).We cannot access the eight temporary registers based on the 3-bit register address available in the instruction.To deal with this problem,we provide,first,4-bit register address from the microinstruction,and second,a microinstruction bit to choose between these addresses and
39、those from the instruction.In addition,the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results of word 文档 可自由复制编辑 operations to be placed directly in memory.To accomplish these goals,we modify the register file by adding the lo
40、gic shown in Figure 10-4(a).the instruction set architecture uses two addresses,one for a source a operand and the other for the other source as well as the destination.The register file uses the B address for a source,and the A and D addresses on the file are connected together,giving the same addr
41、ess for the other source and the destination.Although this reduction from three to two addresses is not essential at the mincroinstruction level,it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats.
42、A quad 2-to-1 multiplexer is attached to each of the two address inputs to the register file,to select between an address from the microinstruction and an address from the instruction.There is a 5-bit field in the microinstruction for the combined destination and source address DSA,in addition to a
43、5-bit field for the B address SB.The first bit of each of the these fields selects between the register file address in the microinstruction(0)and the register file address in the instruction(1).If an instruction address is selected,whether it is DST or SRC is determined by an additional quad 2-to-1
44、 multiplexer.This multiplexer is controlled by the second bit of the DSA or SB fields,depending on which of them has 1 in the first bit in any microinstruction,thereby ensuring that the proper second bit is used to determine the register address.A 0 is appended to the left of the 3-bit fields DST an
45、d SRC to cause them to address R0 through R7.the addition to the first bit,which selects the address source,the addresses from the microinstruction contain four bits so that all 16 registers can be reached.The final change to the register file is to replace the storage elements for R0 in the file wi
46、th open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs.A symbol for the resulting register file is show in Figure 10-4(b).We find that,based on the eight shift instructions provided,the shifter from section 8-10,needs to be modified.Th
47、e modifications involve the end bits of the shift logic.For logical shifts,a 0 is inserted,as before.For the right arithmetic shift,she sign bit is the incoming bit,and for the left arithmetic shift,0 is the incoming bit.Rotates require that the bit from the opposite end of the shifter be fed around
48、.Finally,rotates with carry require that the carry flip-flop output be provide as an input on both ends of the shifter.2.Summary In this paperwe examined two CPU designs:the CISC and RISC.The CISC control unit includes a stack pointer in addition to the program counterControl microprograms reside in
49、 ROMand a combination of a multiplexer and a ROM provides fast instruction decodingThe control unit also has extensiveump and word 文档 可自由复制编辑 conditional branching capabilities，including one level of microsubroutines The microprogram for the control is modularized to permit many microsubroutines to
50、be shared in implementing the microprogram for the instructions The RISC control unit is pipelined and has special hardware added to deal with branches.Pipelined CPUs have both data and control hazard problemsWe examined one of each type of hazard，as well as software and hardware solutions for each