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1、第六章第六章 Verilog HDL高级程序高级程序设计举例设计举例1/27/20231MicroelectronicsSchoolXidianUniversity6.1数字电路系统设计的层次化描述方法数字电路系统设计的层次化描述方法Bottom-Up:1/27/20232MicroelectronicsSchoolXidianUniversity串行加法器:一个四位串行加法器由4个全加器构成。全加器是串行加法器的子模块，而全加器是由基本的逻辑门构成，这些基本的逻辑门就是所说的叶子模块。这个设计中运用叶子模块（基本逻辑门）搭建成子模块（全加器），再用子模块搭建成所需要的电路（串行加法器）。显然
2、，Bottom-Up的设计方法没有明显的规律可循，主要依靠设计者的实践经验和熟练的设计技巧，用逐步试探的方法最后设计出一个完整的数字系统。系统的各项性能指标只有在系统构成后才能分析测试。此种设计方法常用于原理图的设计中，相比于其它方法此种方法对于实现各个子模块电路所需的时间较短。1/27/20233MicroelectronicsSchoolXidianUniversityTop-Down:1/27/20234MicroelectronicsSchoolXidianUniversity使用Top-Down设计方法对一个典型cpu进行设计：1/27/20235MicroelectronicsSc
3、hoolXidianUniversity向量点积乘法器：采用模块层次化设计方法，设计4维向量点积乘法器，其中向量a=（a1，a2，a3，a4）；b=（b1，b2，b3，b4）。点积乘法规则为：1/27/20236MicroelectronicsSchoolXidianUniversity 1/27/20237MicroelectronicsSchoolXidianUniversityVerilogHDL程序代码为：modulevector(a1,a2,a3,a4,b1,b2,b3,b4,out);input3:0a1,a2,a3,a4,b1,b2,b3,b4;output9:0out;wire
4、7:0out1,out2,out3,out4;wire8:0out5,out6;wire9:0out;mul_addtreeU1(.x(a1),.y(b1),.out(out1);mul_addtreeU2(.x(a2),.y(b2),.out(out2);mul_addtreeU3(.x(a3),.y(b3),.out(out3);mul_addtreeU4(.x(a4),.y(b4),.out(out4);add#(8)U5(.a(out1),.b(out2),.out(out5);add#(8)U6(.a(out3),.b(out4),.out(out6);add#(9)U7(.a(ou
5、t5),.b(out6),.out(out);endmodule/addermoduleadd(a,b,out);parametersize=8;inputsize-1:0a,b;outputsize:0out;assignout=a+b;endmodule/Multipliermodulemul_addtree(mul_a,mul_b,mul_out);input3:0mul_a,mul_b;/IOdeclarationoutput7:0mul_out;wire3:0mul_out;/Wiredeclarationwire3:0stored0,stored1,stored2,stored3;
6、wire3:0add01,add23;assignstored3=mul_b3?1b0,mul_a,3b0:8b0;/Logicdesignassignstored2=mul_b2?2b0,mul_a,2b0:8b0;assignstored1=mul_b1?3b0,mul_a,1b0:8b0;assignstored0=mul_b0?4b0,mul_a:8b0;assignadd01=stored1+stored0;assignadd23=stored3+stored2;assignmul_out=add01+add23;endmodule6.2典型电路设计典型电路设计加法器树乘法器加法器树
7、乘法器的设计思想是“移位后加”，并且加法运算采用加法器树的形式。乘法运算的过程是，被乘数与乘数的每一位相乘并且乘以相应的权值，最后将所得的结果相加，便得到了最终的乘法结果。例：下图是一个4位的乘法器结构，用VerilogHDL设计一个加法器树4位乘法器1/27/20238MicroelectronicsSchoolXidianUniversity1/27/20239MicroelectronicsSchoolXidianUniversitymodulemul_addtree(mul_a,mul_b,mul_out);input3:0mul_a,mul_b;/IOdeclarationoutpu
8、t7:0mul_out;wire7:0mul_out;/Wiredeclarationwire7:0stored0,stored1,stored2,stored3;wire7:0add01,add23;assignstored3=mul_b3?1b0,mul_a,3b0:8b0;/Logicdesignassignstored2=mul_b2?2b0,mul_a,2b0:8b0;assignstored1=mul_b1?3b0,mul_a,1b0:8b0;assignstored0=mul_b0?4b0,mul_a:8b0;assignadd01=stored1+stored0;assigna
9、dd23=stored3+stored2;assignmul_out=add01+add23;endmodulemodulemult_addtree_tb;reg3:0mult_a;reg3:0mult_b;wire7:0mult_out;/moduleinstancemul_addtreeU1(.mul_a(mult_a),.mul_b(mult_b),.mul_out(mult_out);initial/Stimulisignalbeginmult_a=0;mult_b=0;repeat(9)begin#20mult_a=mult_a+1;mult_b=mult_b+1;endendend
10、module流水线结构流水线结构例：下图是一个4位的乘法器结构，用VerilogHDL设计一个两级流水线加法器树4位乘法器。两级流水线加法器树4位乘法器结构如图所示，通过在第一级与第二级、第二级与第三级加法器之间插入D触发器组，可以实现两级流水线设计。1/27/202310MicroelectronicsSchoolXidianUniversity1/27/202311MicroelectronicsSchoolXidianUniversitymodulemul_addtree_2_stage(clk,clr,mul_a,mul_b,mul_out);inputclk,clr;input3:0
11、mul_a,mul_b;/IOdeclarationoutput7:0mul_out;reg7:0add_tmp_1,add_tmp_2,mul_out;wire7:0stored0,stored1,stored2,stored3;assignstored3=mul_b3?1b0,mul_a,3b0:8b0;/Logicdesignassignstored2=mul_b2?2b0,mul_a,2b0:8b0;assignstored1=mul_b1?3b0,mul_a,1b0:8b0;assignstored0=mul_b0?4b0,mul_a:8b0;always(posedgeclkorn
12、egedgeclr)/Timingcontrolbeginif(!clr)beginadd_tmp_1=8b0000_0000;add_tmp_2=8b0000_0000;mul_out=8b0000_0000;endelsebeginadd_tmp_1=stored3+stored2;add_tmp_2=stored1+stored0;mul_out=add_tmp_1+add_tmp_2;endendendmodule1/27/202312MicroelectronicsSchoolXidianUniversitymodulemult_addtree_2_stag_tb;regclk,cl
13、r;reg3:0mult_a,mult_b;wire7:0mult_out;mul_addtree_2_stageU1(.mul_a(mult_a),.mul_b(mult_b),.mul_out(mult_out),.clk(clk),.clr(clr);initialbeginclk=0;clr=0;mult_a=1;mult_b=1;#5clr=1;endalways#10clk=clk;initialbeginrepeat(5)begin#20mult_a=mult_a+1;mult_b=mult_b+1;endendendmodule6.2.2 Wallace 树乘法器树乘法器Wal
14、lace树乘法器运算原理如下图所示，其中FA为全加器HA为半加器。其基本原理是，加法从数据最密集的地方开始，不断地反复使用全加器半加器来覆盖“树”。这一级全加器是一个3输入2输出的器件，因此全加器又称为3-2压缩器。通过全加器将树的深度不断缩减，最终缩减为一个深度为2的树。最后一级则采用一个简单的两输入加法器组成。1/27/202313MicroelectronicsSchoolXidianUniversity 1/27/202314MicroelectronicsSchoolXidianUniversitymodulewallace(x,y,out);parametersize=4;/Def
15、ineparametersinputsize-1:0 x,y;output2*size-1:0out;/IOdeclarationwiresize*size-1:0a;wire1:0b0,b1,c0,c1,c2,c3;/Wiredeclarationwire5:0add_a,add_b;wire6:0add_out;wire2*size-1:0out;1/27/202315MicroelectronicsSchoolXidianUniversityassigna=x3,x3,x2,x2,x1,x3,x1,x0,x3,x2,x1,x0,x2,x1,x0,x0&y3,y2,y3,y2,y3,y1,
16、y2,y3,y0,y1,y1,y2,y0,y0,y1,y0;/PrepartmultiplierhaddU1(.x(a8),.y(a9),.out(b0);/2inputhalfadderhaddU2(.x(a11),.y(a12),.out(b1);haddU3(.x(a4),.y(a5),.out(c0);faddU4(.x(a6),.y(a7),.z(b00),.out(c1);/3inputfulladderfaddU5(.x(a13),.y(a14),.z(b01),.out(c2);faddU6(.x(b10),.y(a10),.z(b11),.out(c3);assignadd_
17、a=c31,c21,c11,c01,a3,a1;/adderassignadd_b=a15,c30,c20,c10,c00,a2;assignadd_out=add_a+add_b;assignout=add_out,a0;endmodulemodulefadd(x,y,z,out);output1:0out;inputx,y,z;assignout=x+y+z;endmodulemodulehadd(x,y,out);output1:0out;inputx,y;assignout=x+y;endmodule1/27/202316MicroelectronicsSchoolXidianUniv
18、ersitymodulewallace_tb;reg3:0 x,y;wire7:0out;wallacem(.x(x),.y(y),.out(out);/moduleinstanceinitial/Stimulisignalbeginx=3;y=4;#20 x=2;y=3;#20 x=6;y=8;endendmodule复数乘法器复数乘法的算法是：设复数，则复数乘法结果复数乘法器的电路结构如下图所示。将复数x的实部与复数y的实部相乘，减去x的虚部与y的虚部相乘，得到输出结果的实部。将x的实部与y的虚部相乘，加上x的虚部与y的实部相乘，得到输出结果的虚部。1/27/202317Microelec
19、tronicsSchoolXidianUniversity1/27/202318MicroelectronicsSchoolXidianUniversitymodulecomplex(a,b,c,d,out_real,out_im);input3:0a,b,c,d;output8:0out_real,out_im;wire7:0sub1,sub2,add1,add2;wallace U1(.x(a),.y(c),.out(sub1);wallace U2(.x(b),.y(d),.out(sub2);wallace U3(.x(a),.y(d),.out(add1);wallace U4(.x
20、(b),.y(c),.out(add2);assignout_real=sub1-sub2;assignout_im=add1+add2;endmodulemodulecomplex_tb;reg3:0a,b,c,d;wire8:0out_real;wire8:0out_im;complexU1(.a(a),.b(b),.c(c),.d(d),.out_real(out_real),.out_im(out_im);initialbegina=2;b=2;c=5;d=4;#10a=4;b=3;c=2;d=1;#10a=3;b=2;c=3;d=4;endendmodule6.2.4FIR滤波器设计
21、有限冲激响应（FIR）滤波器就是一种常用的数字滤波器，采用对已输入样值的加权和来形成它的输出。其系统函数为其中z-1表示延时一个时钟周期，z-2表示延时两个时钟周期。对于输入序列Xn的FIR滤波器可用下图所示的结构示意图来表示，其中Xn是输入数据流。各级的输入连接和输出连接被称为抽头，并且系数（b0,b1,bn）被称为抽头系数。一个M阶的FIR滤波器将会有M+1个抽头。通过移位寄存器用每个时钟边沿n（时间下标）处的数据流采样值乘以抽头系数，并将它们加起来形成输出Yn。1/27/202319MicroelectronicsSchoolXidianUniversity 1/27/202320Mic
22、roelectronicsSchoolXidianUniversitymoduleFIR(Data_out,Data_in,clock,reset);output9:0Data_out;input3:0Data_in;inputclock,reset;wire9:0Data_out;wire3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;shift_registerU1(.Data_in(Data_in),.clock(clock),.reset(reset
23、),.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8);caculatorU2(.samples_0(samples_0),.samples_1(samples_1),.samples_2(samples_2),.samples_3(samples_3),
24、.samples_4(samples_4),.samples_5(samples_5),.samples_6(samples_6),.samples_7(samples_7),.samples_8(samples_8),.Data_out(Data_out);endmodule1/27/202321MicroelectronicsSchoolXidianUniversitymoduleshift_register(Data_in,clock,reset,samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,s
25、amples_7,samples_8);input3:0Data_in;inputclock,reset;output3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;reg3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;always(posedgeclockornegedgereset)beginif(reset)begi
26、nsamples_0=4b0;samples_1=4b0;samples_2=4b0;samples_3=4b0;samples_4=4b0;samples_5=4b0;samples_6=4b0;samples_7=4b0;samples_8=4b0;end1/27/202322MicroelectronicsSchoolXidianUniversityelsebeginsamples_0=Data_in;samples_1=samples_0;samples_2=samples_1;samples_3=samples_2;samples_4=samples_3;samples_5=samp
27、les_4;samples_6=samples_5;samples_7=samples_6;samples_8=samples_7;endendendmodulemodulecaculator(samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8,Data_out);input3:0samples_0,samples_1,samples_2,samples_3,samples_4,samples_5,samples_6,samples_7,samples_8;outpu
28、t9:0Data_out;wire9:0Data_out;wire3:0out_tmp_1,out_tmp_2,out_tmp_3,out_tmp_4,out_tmp_5;wire7:0out1,out2,out3,out4,out5;1/27/202323MicroelectronicsSchoolXidianUniversityparameterb0=4b0010;parameterb1=4b0011;parameterb2=4b0110;parameterb3=4b1010;parameterb4=4b1100;mul_addtreeU1(.mul_a(b0),.mul_b(out_tm
29、p_1),.mul_out(out1);mul_addtreeU2(.mul_a(b1),.mul_b(out_tmp_2),.mul_out(out2);mul_addtreeU3(.mul_a(b2),.mul_b(out_tmp_3),.mul_out(out3);mul_addtreeU4(.mul_a(b3),.mul_b(out_tmp_4),.mul_out(out4);mul_addtreeU5(.mul_a(b4),.mul_b(samples_4),.mul_out(out5);assignout_tmp_1=samples_0+samples_8;assignout_tm
30、p_2=samples_1+samples_7;assignout_tmp_3=samples_2+samples_6;assignout_tmp_4=samples_3+samples_5;assignData_out=out1+out2+out3+out4+out5;endmodule1/27/202324MicroelectronicsSchoolXidianUniversitymoduleFIR_tb;regclock,reset;reg3:0Data_in;wire9:0Data_out;FIRU1(.Data_out(Data_out),.Data_in(Data_in),.clo
31、ck(clock),.reset(reset);initialbeginData_in=0;clock=0;reset=1;#10reset=0;endalwaysbegin#5clock=clock;#5Data_in=Data_in+1;endendmodule片内存储器的设计片内存储器的设计（1）RAM的VerilogHDL描述RAM是随机存储器，存储单元的内容可按需随意取出或存入。这种存储器在断电后将丢失掉所有数据，一般用来存储一些短时间内使用的程序和数据。其内部结构如下图所示：1/27/202325MicroelectronicsSchoolXidianUniversity例：用例：
32、用Verilog HDL设计深度为设计深度为8，位宽为，位宽为8的单端口的单端口RAM。单口单口RAM，只有一套地址总线，读操作和写操作是分开的，只有一套地址总线，读操作和写操作是分开的。1/27/202326MicroelectronicsSchoolXidianUniversitymoduleram_single(clk,addm,cs_n,we_n,din,dout);inputclk;/clocksignalinput2:0 addm;/addresssignalinputcs_n;/chipselectsignalinputwe_n;/writeenablesignalinput7:
33、0din;/inputdataoutput7:0dout;/outputdatareg7:0dout;reg7:0raml7:0;/8*8bitesregisteralways(posedgeclk)beginif(cs_n)dout=8bzzzz_zzzz;elseif(we_n)/readdatadout=ramladdm;else/writedataramladdm=din;endendmodule1/27/202327MicroelectronicsSchoolXidianUniversitymoduleram_single_tb;regclk,we_n,cs_n;reg2:0addm
34、;reg7:0din;wire7:0dout;ram_singleU1(.clk(clk),.addm(addm),.cs_n(cs_n),.we_n(we_n),.din(din),.dout(dout);initialbeginclk=0;addm=0;cs_n=1;we_n=0;din=0;#5cs_n=0;#315we_n=1;endalways#10clk=clk;initialbeginrepeat(7)begin#40addm=addm+1;din=din+1;end#40repeat(7)#40addm=addm-1;endendmodule例：用例：用Verilog HDL设
35、计深度为设计深度为8，位宽为，位宽为8的双端口的双端口RAM。双口双口RAM具有两套地址总线，一套用于读数据，另一套用于写数据。具有两套地址总线，一套用于读数据，另一套用于写数据。二者可二者可以分别独立操作。以分别独立操作。1/27/202328MicroelectronicsSchoolXidianUniversitymoduleram_dual(q,addr_in,addr_out,d,we,rd,clk1,clk2);output7:0q;/outputdatainput7:0d;/inputdatainput2:0addr_in;/writedataaddresssignalinput
36、2:0addr_out;/outputdataaddresssignalinputwe;/writedatacontrolsignalinputrd;/readdatacontrolsignalinputclk1;/writedataclockinputclk2;/readdataclockreg7:0q;reg7:0mem7:0;/8*8bitesregisteralways(posedgeclk1)beginif(we)memaddr_in=d;endalways(posedgeclk2)beginif(rd)q=memaddr_out;endendmodule1/27/202329Mic
37、roelectronicsSchoolXidianUniversitymoduleram_dual_tb;regclk1,clk2,we,rd;reg2:0addr_in;reg2:0addr_out;reg7:0d;wire7:0q;ram_dualU1(.q(q),.addr_in(addr_in),.addr_out(addr_out),.d(d),.we(we),.rd(rd),.clk1(clk1),.clk2(clk2);initialbeginclk1=0;clk2=0;we=1;rd=0;addr_in=0;addr_out=0;d=0;#320we=0;rd=1;endalw
38、aysbegin#10clk1=clk1;clk2=clk2;endinitialbeginrepeat(7)begin#40addr_in=addr_in+1;d=d+1;end#40repeat(7)#40addr_out=addr_out+1;endendmodule（2）ROM的VerilogHDL描述ROM即只读存储器，是一种只能读出事先存储的数据的存储器，其特性是存入数据无法改变，也就是说这种存储器只能读不能写。由于ROM在断电之后数据不会丢失，所以通常用在不需经常变更资料的电子或电脑系统中，资料并不会因为电源关闭而消失。1/27/202330MicroelectronicsSch
39、oolXidianUniversitymodulerom(dout,clk,addm,cs_n);inputclk,cs_n;input2:0addm;output7:0dout;reg7:0dout;reg7:0rom7:0;initialbeginrom0=8b0000_0000;rom1=8b0000_0001;rom2=8b0000_0010;rom3=8b0000_0011;rom4=8b0000_0100;rom5=8b0000_0101;1/27/202331MicroelectronicsSchoolXidianUniversityrom6=8b0000_0110;rom7=8
40、b0000_0111;endalways(posedgeclk)beginif(cs_n)dout=8bzzzz_zzzz;elsedout=romaddm;endendmodulemodulerom_tb;regclk,cs_n;reg2:0addm;wire7:0dout;romU1(.dout(dout),.clk(clk),.addm(addm),.cs_n(cs_n);initialbeginclk=0;addm=0;cs_n=0;endalways#10clk=clk;initialbeginrepeat(7)#20addm=addm+1;endendmodule6.2.6 FIF
41、O设计设计FIFO（FirstInFirstOut）是一种先进先出的数据缓存器，通常用于接口电路的数据缓存。与普通存储器的区别是没有外部读写地址线，可以使用两个时钟分别进行写和读操作。FIFO只能顺序写入数据和顺序读出数据，其数据地址由内部读写指针自动加1完成，不能像普通存储器那样可以由地址线决定读取或写入某个指定的地址。FIFO由存储器块和对数据进出FIFO的通道进行管理的控制器构成，每次只对一个寄存器提供存取操作，而不是对整个寄存器阵列进行。FIFO有两个地址指针，一个用于将数据写入下一个可用的存储单元，一个用于读取下一个未读存储单元的操作。读写数据必须一次进行。1/27/202332Mi
42、croelectronicsSchoolXidianUniversity其读写过程如下图所示：1/27/202333MicroelectronicsSchoolXidianUniversity当一个堆栈为空时（图A），读数据指针和写数据指针都指向第一个存储单元，如所示；当写入一个数据时（图B）写数据指针将指向下个存储单元；经过七次写数据操作后（图C）写指针将指向最后一个数据单元；当经过连续八次写操作之后写指针将回到首单元并且显示堆栈状态为满（图D）。数据的读操作和写操作相似，当读出一个数据时，读数据指针将移向下一个存储单元，直到读出全部的数据，此时读指针回到首单元，堆栈状态显示为空。一个FIF
43、O的组成一般包括两个部分：地址控制部分和存储数据的RAM部分。如下图所示。地址控制部分可以根据读写指令生成RAM地址。RAM用于存储堆栈数据，并根据控制部分生成的地址信号进行数据的存储和读取操作。这里的RAM采用的是前面提到的双口RAM。1/27/202334MicroelectronicsSchoolXidianUniversity1/27/202335MicroelectronicsSchoolXidianUniversity例：用VerilogHDL设计深度为8，位宽为8的FIFO/顶层模块：moduleFIFO_buffer(clk,rst,write_to_stack,read_fr
44、om_stack,Data_in,Data_out);inputclk,rst;inputwrite_to_stack,read_from_stack;input7:0Data_in;output7:0Data_out;wire7:0Data_out;wirestack_full,stack_empty;wire2:0addr_in,addr_out;FIFO_controlU1(.stack_full(stack_full),.stack_empty(stack_empty),.write_to_stack(write_to_stack),.write_ptr(addr_in),.read_
45、ptr(addr_out),.read_from_stack(read_from_stack),.clk(clk),.rst(rst);ram_dualU2(.q(Data_out),.addr_in(addr_in),.addr_out(addr_out),.d(Data_in),.we(write_to_stack),.rd(read_from_stack),.clk1(clk),.clk2(clk);endmodule1/27/202336MicroelectronicsSchoolXidianUniversity/控制模块：moduleFIFO_control(write_ptr,re
46、ad_ptr,stack_full,stack_empty,write_to_stack,read_from_stack,clk,rst);parameterstack_width=8;parameterstack_height=8;parameterstack_ptr_width=3;outputstack_full;/stackfullflagoutputstack_empty;/stackemptyflagoutputstack_ptr_width-1:0read_ptr;/readdataaddressoutputstack_ptr_width-1:0write_ptr;/writed
47、ataaddressinputwrite_to_stack;/writedatatostackinputread_from_stack;/readdatafromstackinputclk;inputrst;regstack_ptr_width-1:0read_ptr;regstack_ptr_width-1:0write_ptr;regstack_ptr_width:0ptr_gap;regstack_width-1:0Data_out;regstack_width-1:0stackstack_height-1:0;1/27/202337MicroelectronicsSchoolXidia
48、nUniversity/stackstatussignalassignstack_full=(ptr_gap=stack_height);assignstack_empty=(ptr_gap=0);always(posedgeclkorposedgerst)beginif(rst)beginData_out=0;read_ptr=0;write_ptr=0;ptr_gap=0;endelseif(write_to_stack&(!stack_full)&(!read_from_stack)beginwrite_ptr=write_ptr+1;ptr_gap=ptr_gap+1;endelsei
49、f(!write_to_stack&(!stack_empty)&(read_from_stack)beginread_ptr=read_ptr+1;ptr_gap=ptr_gap-1;end1/27/202338MicroelectronicsSchoolXidianUniversityelseif(write_to_stack&stack_empty&read_from_stack)beginwrite_ptr=write_ptr+1;ptr_gap=ptr_gap+1;endelseif(write_to_stack&stack_full&read_from_stack)beginrea
50、d_ptr=read_ptr+1;ptr_gap=ptr_gap-1;endelseif(write_to_stack&read_from_stack&(!stack_full)&(!stack_empty)beginread_ptr=read_ptr+1;write_ptr=write_ptr+1;endendendmodule1/27/202339MicroelectronicsSchoolXidianUniversitymoduleFIFO_tb;regclk,rst;reg7:0Data_in;regwrite_to_stack,read_from_stack;wire7:0Data_