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1、Cadence 后端实验系列后端实验系列19_版图验证版图验证_ AssuraIntroduction to Assura Physical VerificationAssura Physical Verification Tool SuiteAssura Task and Data FlowAssura Input FilesRunning Assura DRC Graphical User Interface Run GuideLVS Graphical User Interface Run GuideRCX Graphical User Interface Run GuideDemons
2、trationOUTLINEIntroduction to Assura Physical VerificationAssura Physical Verification Tool SuiteAssura Task and Data FlowAssura Input FilesRunning Assura DRC Graphical User Interface Run GuideLVS Graphical User Interface Run GuideRCX Graphical User Interface Run GuideDemonstrationOUTLINEAssura Phys
3、ical Verification Tool SuiteThe Assura verification suite is optimized for large,hierarchical,repetitive designs such as memory,microprocessor,and mixed-signal circuits.The software upholds the Cadence verification tradition of accuracy established by its Dracula and Diva products.The Assura tools e
4、nsure accuracy and leverage the layout hierarchy of leading-edge designs to provide faster physical verification runtimes.Assura Physical Verification Tool SuiteAssura DRC Assura DRC(Design Rule Checking)checks the layout against geometric spacing,width,and other rules.Typical checks include materia
5、l spacing,enclosure,coverage,and overlap.Assura DRC displays design rule violations graphically as an additional graphics layer on the layout,and lists them in text files.Assura LVS Assura LVS(Layout Versus Schematic)comparison extracts devices and connectivity from the layout according to device ex
6、traction rules,then creates a layout netlist according to netlist rules,then finally compares the layout netlist to the schematic netlist according to comparison rules.Assura LVS displays mismatches between the layout and the schematic both textually and graphically.Assura RCX Assura RCX(Resistance,
7、Capacitance and Inductance Extraction)extracts parasitic resistance,capacitance,and inductance from the layout for analysis and input to post-layout simulators.Assura Task and Data FlowAssura Input FilesRun-Specific File(RSF)The Assura RSF is a required control file in text format that directs the A
8、ssura DRC,LVS,or RCX run.It specifies input data files,rule files,run-specific options,and commands to invoke the tool.The Assura RSF follows Cadence SKILL language syntax.Options in an RSF are specified as parameters,which begin with a“?”followed by a keyword.When you use the Assura Graphical User
9、Interface(GUI),the GUI creates the RSF for you using the settings you specified in the forms,and invokes an Assura tool using this RSF.Alternatively you can create your own RSF.You can specify the RSF file name in the GUI run form,or you can specify the RSF file name on the command line if you run a
10、n Assura tool in batch mode.Run-Specific File(RSF)The Assura RSF consists of several sections:A mandatory avParameters sectionOne or more avCompareRules sections for an LVS runAn rcxParameters section for an RCX runOptional statements outside the above sectionsOne or more mandatory Assura tool invoc
11、ation commandsThe avParameters SectionThe Assura RSF contains a mandatory avParameters section that specifies the input layout and rules file associated with the Assura run,plus various global RSF options.Below is an example of an avParameters section.avParameters(?workingDirectory/usr1/drc/“?runNam
12、e peakDetect?inputLayout(df2 design)?cellName peakDetect?technology“gold“?techLib/usr1/amancuso/rcx/assura_tech.lib“)The avCompareRules SectionThe RSF contains one or more avCompareRules sections if the RSF is for an Assura LVS run.The avCompareRules section Specifies the input schematic,an optional
13、 binding file for mapping layout device and net names to schematic names,and other rules and options.avCompareRules(schematic(netlist(dfII“netlist.dfII”)bindingFile(“bindings”)mergeSplitGate(mergeAll)showErrorNetwork()compareParameter(MOS percent(“w”5“l”5)compareParameter(res_poly percent(r 5)compar
14、eParameter(res_nwell percent(r10)The rcxParameters SectionThe RSF contains an rcxParameters section if the RSF is for an RCX run.rcxParameters(?runNamepeakDetect?extractcap?minR0.001?maxFractureLengthinfinite?fractureLengthUnitsmicrons?capExtractModedecoupled?capGroundvss!?capCouplingFactor1.0?typef
15、ull?netNameSpacelayout?outputFormatspice?outputpeakDetect.sp?groundNets (vss!gnd!)?powerNets (vdd!)?tempdir /tmp?parasiticResModels comment?subNodeChar#?outputNetNameSpace schematic?parasiticCapModels yes?capModels no?hierarchyDelimiter /?resModels no)RSF Statements Outside SectionsYou can place opt
16、ional statements in the RSF outside an avParameters,avCompareRules or rcxParameters section.These statements include several Assura rules that can optionally be placed in an RSF,user-supplied SKILL functions,and Assura tool invocation commands.Assura Tool Invocation CommandsThe Assura RSF must end w
17、ith one or more Assura tool invocation commands that launch the appropriate verification tasks.When an Assura tool is run from the GUI,the appropriate invocation command is placed at the end of the RSF.If you create your own RSF,you can nest parameter sections within the invocation command to specif
18、y parameters that apply to that command only.Command DescriptionavDRCRuns the DRC tool.Outputs can include a DRC error database and a layout database with original,derived,and generated layers.avDRC is controlled by avParameters,DRC rules,and a layout.Command DescriptionavDX()Runs the DRC and device
19、 extraction tools.Outputs can include:a DRC error database a layout database with original,derived,and generated layers extracted devices in an internal format that avNX can use as input avDX requires avParameters,DRC rules,device and connectivity extraction rules,and a layout.avExtract()Produces an
20、 extracted circuit in DFII extracted view or SPICE format with layout information only,with or without parasitic information.Runs avDX and avNX,and optionally avRCX.avExtract requires avParameters,rcxParameters,extraction rules,and a layout.avExtract does not require a schematic specification.avNX()
21、Runs the LVS net extraction tool to produce a layout netlist in Assura database(VLDB)format.avNX requires avParameters,extractionrules,and a device extraction database(output from avDX).Command DescriptionavNVN()Runs the LVS netlist list comparison tool.avNX requires avParameters,avCompareRules,sche
22、matic netlisting rules,a layout netlist,and a DFII schematic or a schematic netlist.avLVS()Runs the LVS tool,which includes avDX,avNX and avNVN.avRCX()Runs the parasitic extraction(RCX)tool to produce parasitic device information in several formats.avRCX requires avParameters,rcxParameters,and a lay
23、out.Rule FilesAssura tools require a set of rules to guide their operation.Rule files are text files.Rules are grouped together in the rule file within separate sections enclosed in parentheses.Assura rules follow the syntax of the Cadence SKILL programming language.Assura rule files can be located
24、anywhere in your file system,and they do not have default names.The following table lists the standard rule files used with each tool:ToolRule File(s)DRCdrc.rul:contains rules for layout width and separation checksLVSextract.rul:contains rules for defining and extracting devices and nets from the la
25、yout datacompare.rul:contains rules for comparing the schematic netlist to the extracted layout netlistbinding.rul:optional binding rules to help Assura LVS match the schematic to layoutdeviceinfo.rul:a support file that can be used to import a schematic netlistRCXprocess file:contains the layer sta
26、ckup specification and design rules for the specific fabrication technology of the design.runName.xcn:the LVS extract.rul file converted into a format compatible with capgenp2lvsfile:a mapping file that associates one or more LVS layers specified in the extract.rul to a single layer specified in the
27、 process file.Assura DRC RulesWithin an Assura drc.rul file,DRC rules are contained in a drcExtractRules section.drcExtractRules(layerDefs(df2nwell=layer(nwell type(drawing)poly1=layer(poly1 type(drawing)pwell=layer(pwell type(drawing)metal1=layer(metal1 type(drawing)metal2=layer(metal2 type(drawing
28、)contact=layer(cont type(drawing)via=layer(via type(drawing)ndiff=layer(ndiff type(drawing)pdiff=layer(pdiff type(drawing)text=text(text type(drawing);end layerDefslayerDefs(gds2nwell=layer(12)poly1=layer(35)pwell=layer(6)metal1=layer(45)metal2=layer(50)contact=layer(55)via=layer(8)ndiff=layer(1)pdi
29、ff=layer(2)text=text(62);end layerDefsThe first step is identifying the physical design layers contained in the input layout data.Layer Definition RulesLayer Derivation Rulesngate=geomAnd(ndiff poly1)ngate layer=ndiff AND poly1pgate=geomAnd(pdiff poly1)ndiff=geomAndNot(ndiff poly1)pdiff=geomAndNot(p
30、diff poly1);pdiff=orig pdiff not including pdiff under poly1ptap=geomAndNot(pdiff nwell);ptap=derived pdiff less pdiff in nwellntap=geomAnd(ndiff nwell)The next step in specifying DRC rules is to derive additional layers from the original input layers to allow the tool to test the design against spe
31、cific foundry requirements.The Assura program provides several logical operation rules that can be applied to existing layers to derive new layers.For example,MOSFET gate regions,well taps and substrate ties,as well as the substrate bulk,can be derived from the original layer information with Assura
32、 logical operation rules(layer derivation rules also are called layer processing rules).DRC Design Check RulesFollowing is a sample list of design checks for poly1 and metal1 layers.check poly1errpolysep=drc(poly1 sep1 poly1 spacing lt 1)errorLayer(errpolysep)errpolywid=drc(poly1 width1 poly1 width
33、lt 1)errorLayer(errpolywid)errpolynotch=drc(poly1 notch1 poly1 notch lt 1)errorLayer(errpolynotch)errpolycont=drc(poly1 contact enc .5 poly1/contact enclosure lt.75)errorLayer(errpolycont)errpolydiffsep=drc(poly1 diff sep 1 poly1/diff spacing lt 1)errorLayer(errpolydiffsep)end poly1 checkscheck meta
34、l1errmet1sep=drc(metal1 sep1 metal1 spacing lt 1)errorLayer(errmet1sep)drc(metal1 width1 metal1 width lt 1)drc(metal1 notch1 metal1 notch lt 1)drc(metal1 contact enc .5 metal1/contact enclosure error)drc(metal1 via enc .5 Metal1/via enclosure error)end metal1 checksDRC Design Check RulesAssura LVS R
35、ulesLVS Extract RulesThe LVS extract rules,typically contained in an extract.rul file,contain the information necessary for Assura LVS to extract drawn devices and connectivity information from the layout geometry data input to Assura LVS.This extracted device and connectivity information is output
36、by the Assura program in a layout netlist,which Assura LVS compares to the input schematic netlist.LVS Connectivity RulesConnectivity rules are added to the drcExtractRules section to establish connectivity between the defined and derived layout layers.Among other rules,the geomConnect and geomStamp
37、 commands are used for this purposeFor example:geomConnect(via(cont poly1 ndiff pdiff metal1 ntap ptap)via(via metal1 metal2)label(text poly1 metal1 metal2)label(polytext poly1)label(met1text metal1)label(met2text metal2)geomStamp(psubcon ptap error)geomStamp(nwellcon ntap error)LVS Device Extractio
38、n RulesDevice extraction rules are added to the drcExtractRules section of the LVS extract.rul file.These rules tell Assura LVS how to extract specific devices,such as MOSFETs,LDDs,and BJTs,and their associated device terminals,from the defined layout layers.For example:extractMOS(nfet ngate poly1(G
39、)ndiff(S D)psubcon(B)1flagMalformed)extractMOS(pfet pgate poly1(G)pdiff(S D)nwellcon(B)1 flagMalformed)LVS Parameter Extraction RulesAdditional extract rules can be added to the drcExtractRules section to direct Assura LVS to measure and extract layout device parameters,such as MOSFET width and leng
40、th parameters.LVS Compare RulesAssura LVS comparison rules include all the rules associated with comparing a layout netlist to a schematic netlist.The rules include run control options,input schematic specification,and rules governing device parameter comparison.avParameters(?inputLayout()?cellName(
41、);end of avParametersavCompareRules(general_rulesschematic(;netlist specification-requirednetlist()other network_specific_rules)layout(network_specific_rules)bindingFile(/usr1/gold_tech/bind.rul);end of avCompareRulesAssura RCX RulesThere are three primary data files used to define the RCX rules:1.T
42、he process file,which provides technology-based capacitance modeling information2.The lvsfile,which is a converted LVS extract.rul file that provides LVS device and connectivity information to Assura RCX3.The p2lvsfile,which matches the process file to the lvsfile,and also provides technology-based
43、resistance modeling informationRunning AssuraYou can run Assura as an interactive graphical tool or as a batch tool from the Unix command line.Assura requires a text input file called the run-specific file(RSF)for each run.When you use the Assura graphical user interface(GUI),the GUI creates the RSF
44、 and starts the Assura run.When you start Assura as a batch tool you must specify an RSF.Run Mode Assura Start CommandInteractive mode from Virtuoso Layout EditingwindowAssura Run DRCAssura Run LVSStandalone graphical mode from Unix command lineavviewNon-graphical batch modefrom Unix command lineass
45、ura rsf_filenameRunning Assura Tools From the DFII GUILaunch the Cadence DFII executable(icfb)Select File-Open.from the DFII Command Interpreter Window(CIW)as shown below.Select the library,and top cell name of the design,then select layout view,then click OK to open the layout view in the Virtuoso
46、Layout Editor(see below).After you have selected the design,the layout view opens in the Virtuoso layout editor.Running Assura Tools From the DFII GUIRunning Assura Tools From the DFII GUIIntroduction to Assura Physical VerificationAssura Physical Verification Tool SuiteAssura Task and Data FlowAssu
47、ra Input FilesRunning Assura DRC Graphical User Interface Run GuideLVS Graphical User Interface Run GuideRCX Graphical User Interface Run GuideDemonstrationOUTLINEDRC Run GuideDRC Run GuideDRC Run GuideCell name is the name of the top cell of the layout you want to verify.Input File name is the file
48、 containing the Stream design to check.This field is available only if you select Stream as the layout format.DRC Run Guide Run Name is the Name you want to use to refer to this Assura DRC run.If you do not specify a run name,the Assura program uses the cell name of the design.All output files conta
49、in this name as a prefix.Run Directory is the full or relative path to the run directory.If the directory you specify does not exist,Assura DRC creates the directory.Run Location is where you can select either a local or remote machine for a DRC run.DRC Run GuideSwitch NamesIdentifies the section of
50、 statements in the rules file that you want to use for a specific Assura DRC or circuit extraction to control the command stream.To identify the switches that you want to use for an Assura DRC run,type the switch names in the Switch Names field.You must type at least one space between multiple switc