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1、GAIN(dB)06539-001 06539-011 低成本有源低成本有源 RF 分路器分路器 ADA4304 特性特性参数参数应用应用详解详解及及样片样片申请申请指南指南 ADA4304-2（样片申请信息查询：）是一款 75 有源分路器，适合要求无损信号分离的应用。典型应用包括多调谐器数字机顶盒、有线分路器模块、多调谐器/支持数字有线功能(DCR)的电视以及家庭网关。FEATURES FUNCTIONAL BLOCK DIAGRAM Ideal for CATV and terrestrial applications Excellent frequency response 1.6 GH
2、z,3 dB bandwidth 1 dB flatness to 1.0 GHz Low noise figure:4.0 dB Low distortion Composite second order(CSO):62 dBc Composite triple beat(CTB):72 dBc 0.1F 5V VCC 5V 1H IL 0.1F VOUT1 1 dB compression point of 8.25 dBm 2.8 dB of gain per output channel 25 dB output-to-output isolation,50 MHz to 1000 M
3、Hz 75 input and outputs Integrated output resistors Small package size:16-lead,3 mm 3 mm LFCSP APPLICATIONS Set-top boxes Residential gateways CATV distribution systems Splitter modules Digital cable ready(DCR)TVs 0.01F VIN ADA4304-2 VOUT2 GND Figure 1.0.01F 0.01F GENERAL DESCRIPTION The ADA4304-2 i
4、s a 75 active splitter for use in applications where a lossless signal split is required.Typical applications include multituner digital set-top boxes,cable splitter modules,multituner/digital cable ready(DCR)televisions,and home gateways where traditional solutions require discrete passive splitter
5、 modules with separate fixed gain amplifiers.The ADA4304-2 is fabricated using Analog Devices,Inc.proprietary silicon-germanium(SiGe),complementary bipolar process,enabling it to achieve very low levels of distortion with a noise figure of 4 dB.The part provides a low cost alternative that simplifie
6、s designs and improves system performance by integrating a signal splitter element and a gain block into a single 4 3 2 1 TA=+85C 0 1 2 3 4 5 6 7 8 TA=+25C TA=40C IC.The ADA4304-2 is available in a 16-lead LFCSP and operates in the extended industrial temperature range of 40C to+85C.50 100 1000 4000
7、 FREQUENCY(MHz)Rev.0|Page 2 of 12 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）TABLE OF CONTENTS Features.1 Applications.1 Functional Block Diagram.1 General Description.1 Revision History.2 Specifications.3 Absolute Maximum Ratings.4 Thermal Resistance.4 ESD Caution.4 Pin Configuration and Function Descriptio
8、ns.5 Typical Performance Characteristics.6 Test Circuits.8 Applications.9 Circuit Description.9 Evaluation Boards.9 RF Layout Considerations.9 Power Supply.9 Outline Dimensions.11 Ordering Guide.11 REVISION HISTORY 5/07Revision 0:Initial Version 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Rev.0|Page 3 of 12 S
9、PECIFICATIONS VCC=5 V,75 system,TA=25C,unless otherwise noted.Table 1.Parameter Conditions Min Typ Max Unit DYNAMIC PERFORMANCE Bandwidth(3 dB)Specified Frequency Range Gain(S21,S31)1 dB Gain Flatness f=100 MHz;see Figure 17 and Figure 18 1600 54 865 2.8 1000 MHz MHz dB MHz NOISE/DISTORTION PERFORMA
10、NCE Noise Figure1 Output IP3 Output IP2 Composite Triple Beat(CTB)Composite Second Order(CSO)Cross Modulation(CXM)54 MHz 550 MHz 865 MHz f1=97.25 MHz,f2=103.25 MHz f1=97.25 MHz,f2=103.25 MHz 135 channels,15 dBmV/channel,f=865 MHz 135 channels,15 dBmV/channel,f=865 MHz 135 channels,15 dBmV/channel,10
11、0%modulation 15.75 kHz,f=865 MHz 4.0 4.5 4.6 26 44.5 72 62 69 dB dB dB dBm dBm dBc dBc dBc INPUT CHARACTERISTICS Input Return Loss(S11)Output-to-Input Isolation(S12,S13)See Figure 17,Figure 18,and Figure 19 54 MHz 550 MHz 865 MHz Either output,54 MHz to 865 MHz 54 MHz 550 MHz 865 MHz 15 11 35.5 22 1
12、3.3 8 32 30 32 29 33 31 dB dB dB dB dB dB OUTPUT CHARACTERISTICS Output Return Loss(S22,S33)Output-to-Output Isolation(S23,S32)1 dB Compression(P1dB)See Figure 17,Figure 18,and Figure 19 Either output,54 MHz to 865 MHz 54 MHz 550 MHz 865 MHz Either output,54 MHz to 865 MHz 54 MHz 550 MHz 865 MHz Out
13、put referred,f=100 MHz 26.7 21 22 15 20 12 26.7 25.1 25 8.25 dB dB dB dB dB dB dB dBm POWER SUPPLY Nominal Supply Voltage Quiescent Supply Current 4.75 5.0 5.25 88 105 V mA 1 Characterized with 50 noise figure analyzer.Rev.0|Page 4 of 12 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Package Type JA Unit 16-Lead
14、 LFCSP(Exposed Pad)98 C/W MAXIMUM POWER DISSIPATION(W)06539-004 ABSOLUTE MAXIMUM RATINGS Table 2.Parameter Rating Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature(Soldering,10 sec)Junction Temperature 5.5 V See Figure 3 65C to+125C 40C to+85C 30
15、0C 150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.This is a stress rating only;functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied.Exposure
16、to absolute maximum rating conditions for extended periods may affect device reliability.THERMAL RESISTANCE JA is specified for the device(including exposed pad)soldered to a high thermal conductivity 2s2p circuit board,as described in EIA/JESD 51-7.Table 3.Thermal Resistance The power dissipated in
17、 the package(PD)is essentially equal to the quiescent power dissipation;the supply voltage(VS)times the quiescent current(IS).In Table 1,the maximum power dissipation of the ADA4304-2 can be calculated as PD(MAX)=5.25 V 105 mA=551 mW Airflow increases heat dissipation,effectively reducing JA.In addi
18、tion,more metal directly in contact with the package leads/exposed pad from metal traces,through-holes,ground,and power planes reduces the JA.Figure 3 shows the maximum safe power dissipation in the package vs.the ambient temperature for the 16-lead LFCSP(98C/W)on a JEDEC standard 4-layer board.2.0
19、1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Maximum Power Dissipation 0 0 10 20 30 40 50 60 70 80 90 AMBIENT TEMPERATURE(C)100 The maximum safe power dissipation in the ADA4304-2 package is limited by the associated rise in junction temperature(TJ)on the die.At approximately 150C,which is the glass transiti
20、on temperature,the plastic changes its properties.Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die,permanently shifting the parametric performance of the ADA4304-2.Exceeding a junction temperature of 150C for an extended period can result i
21、n changes in the silicon devices,potentially causing failure.Figure 3.Maximum Power Dissipation vs.Temperature for a 4-Layer Board ESD CAUTION 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Rev.0|Page 5 of 12 GND 5 GND 6 GND 7 NC 8 16 VCC 15 VCC 14 IL 13 NC 06539-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V
22、CC 1 VCC 2 GND 3 VIN 4 PIN 1 INDICATOR ADA4304-2 TOP VIEW(Not to Scale)12 VOUT1 11 GND 10 VOUT2 9 GND NC=NO CONNECT Figure 4.Pin Configuration Table 4.Pin Function Descriptions Pin No.Mnemonic Description 1,2,15,16 3,5 to 7,9,11 4 8,13 10 12 14 VCC GND VIN NC VOUT2 VOUT1 IL Supply Pin Ground Input N
23、o Connection Output 2 Output 1 Bias Pin Rev.0|Page 6 of 12 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）CXM(dBc)CTB(dBc)CSO(dBc)06539-006 06539-007 06539-005 OUTPUT IP3(dBm)OUTPUT IP2(dBm)NOISE FIGURE(dB)06539-010 06539-009 06539-008 TYPICAL PERFORMANCE CHARACTERISTICS VCC=5 V,75 system,TA=25C,unless otherwise
24、 noted.54 56 10 50 SYSTEM 58 8 60 62 64 TA=+85C 6 TA=+85C TA=+25C 66 68 70 TA=40C 4 TA=+25C 2 TA=40C 72 74 50 100 FREQUENCY(MHz)1000 0 50 100 FREQUENCY(MHz)1000 Figure 5.Composite Second Order(CSO)vs.Frequency Figure 8.Noise Figure vs.Frequency 60 60 63 66 69 72 75 55 50 45 TA=+85C 40 78 81 84 87 TA
25、=40C TA=+25C 35 30 25 90 50 100 FREQUENCY(MHz)1000 20 50 100 FREQUENCY(MHz)1000 Figure 6.Composite Triple Beat(CTB)vs.Frequency Figure 9.Output IP2 vs.Frequency 60 63 66 69 72 75 78 81 84 87 40 35 30 25 TA=+85C 20 15 TA=40C TA=+25C 10 5 90 50 100 FREQUENCY(MHz)1000 0 50 100 FREQUENCY(MHz)1000 Figure
26、 7.Cross Modulation(CXM)vs.Frequency Figure 10.Output IP3 vs.Frequency 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Rev.0|Page 7 of 12 ISOLATION(dB)ISOLATION(dB)GAIN(dB)06539-013 06539-012 06539-011 QUIESCENT SUPPLY CURRENT(mA)OUTPUT RETURN LOSS(dB)INPUT RETURN LOSS(dB)06539-016 06539-015 06539-014 4 3 2 1 TA=
27、+85C 0 1 2 3 4 5 6 7 8 TA=+25C TA=40C 0 5 10 15 20 25 30 35 40 50 100 1000 4000 FREQUENCY(MHz)50 100 FREQUENCY(MHz)1000 Figure 11.Gain(S21,S31)vs.Frequency Figure 14.Input Return Loss(S11)vs.Frequency 30 31 32 33 34 0 5 10 15 35 20 36 25 37 38 39 30 35 40 50 100 1000 4000 FREQUENCY(MHz)40 50 100 FRE
28、QUENCY(MHz)1000 Figure 12.Output-to-Input Isolation(S12,S13)vs.Frequency Figure 15.Output Return Loss(S22,S33)vs.Frequency 0 95 5 90 10 15 85 20 25 80 30 35 75 40 45 50 100 1000 4000 FREQUENCY(MHz)70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE(C)Figure 13.Output-to-Output Isolatio
29、n(S23,S32)vs.Frequency Figure 16.Quiescent Supply Current vs.Temperature Rev.0|Page 8 of 12 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）06539-019 06539-017 06539-018 TEST CIRCUITS RF NETWORK ANALYZER 75 S-PARAMETER TEST SET VOUT1 VIN PORT 1 12 4 DUT 10 PORT 2 VOUT2 PORT 3 75 Figure 17.Test Circuit for S11,S12
30、,S21,S22 Measurements RF NETWORK ANALYZER 75 S-PARAMETER TEST SET VIN PORT 1 12 4 DUT 10 VOUT1 PORT 2 VOUT2 75 PORT 3 Figure 18.Test Circuit for S13,S31,S33 Measurements RF NETWORK ANALYZER 75 S-PARAMETER TEST SET VIN PORT 1 75 12 4 DUT 10 VOUT1 PORT 2 VOUT2 PORT 3 Figure 19.Test Circuit for S23,S32
31、 Measurements 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Rev.0|Page 9 of 12 5 6 VCC GND VCC GND IL GND NC NC 06539-003 APPLICATIONS The ADA4304-2 active splitter is primarily intended for use in the downstream path of television set-top boxes(STBs)that contain multiple tuners.It is typically located directly
32、 after the diplexer in a bidirectional CATV customer premise unit.The ADA4304-2 provides a single-ended input and two single-ended outputs that allow the delivery of the RF signal to two different signal paths.These paths can include,but are not limited to,a main picture tuner,the picture-in-picture
33、(PIP)tuner,an out-of-band(OOB)tuner,a digital video recorder(DVR),and a cable modem(CM).The ADA4304-2 exhibits composite second order(CSO)and composite triple beat(CTB)products that are 62 dBc and 72 dBc,respectively.The use of the SiGe bipolar process also allows the ADA4304-2 to achieve a noise fi
34、gure(NF)of 4 dB.CIRCUIT DESCRIPTION The ADA4304-2 consists of a low noise buffer amplifier followed by a resistive power divider.This arrangement provides 2.8 dB of gain relative to the RF signal present at the input of the device.The input and each output must be properly matched to a 75 environmen
35、t for distortion and noise performance to match the data sheet specifications.AC coupling capacitors of 0.01 F are recommended for the input and outputs.A 1 H RF choke(Coilcraft chip inductor 0805LS-102X)is required to correctly bias internal nodes of the ADA4304-2.It should be connected between the
36、 5 V supply and the IL pin(Pin 14).The choke should be placed as close as possible to the ADA4304-2 to minimize parasitic capacitance on the IL pin,which is critical for achieving the specified bandwidth and flatness.EVALUATION BOARDS The ADA4304-2 evaluation board allows designers to assess the per
37、formance of the parts in their particular application.The board includes 75 coaxial connectors and 75 controlled-impedance signal traces that carry the input and output signals.Power(5 V)is applied to the red VCC loop connector,and ground is connected to the black GND loop connector.Figure 20 is a s
38、chematic of the ADA4304-2 evaluation board.On the ADA4304-2 evaluation board,connectors VO1 and VO4 are not populated.RF LAYOUT CONSIDERATIONS Appropriate impedance matching techniques are mandatory when designing circuit boards for the ADA4304-2.Improper characteristic impedances on traces can caus
39、e reflections that can lead to poor linearity.The characteristic impedance of the signal trace to the input and from each output should be 75.Any ground metal on the top surface near signal lines should be stitched with vias to the internal ground plane,as shown in Figure 21.POWER SUPPLY The 5 V sup
40、ply should be applied to each of the VCC pins and RF choke via a low impedance power bus.The power bus should be decoupled to ground using a 10 F tantalum capacitor and a 0.1 F ceramic chip capacitor located close to the ADA4304-2.In addition,the VCC pins should be decoupled to ground with a 0.1 F c
41、eramic chip capacitor located as close to each of the pins as possible.GND VCC C5 +10F L1 1.0H C1 0.1F C8 0.1F 16 15 1 VCC 2 VCC 14 13 12 VOUT1 11 GND C3 0.01F C4 VO2 VIN C2 0.01F 3 GND 4 VIN ADA4304-2 10 VOUT2 9 GND 0.01F VO3 7 8 NC=NO CONNECT Figure 20.Evaluation Board Schematic Rev.0|Page 10 of 1
42、2 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）06539-020 06539-021 Figure 21.ADA4304-2 Evaluation Board Figure 22.Evaluation Board Component Layout 国内外 65 家 IC 厂商免费样片查询：ICTry 样片申请网（）Rev.0|Page 11 of 12 OUTLINE DIMENSIONS 3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR 1.25 PIN 1 TOP 2.75 0.45 13 12 16 1 1.
43、10 SQ 0.95 INDICATOR VIEW BSC SQ EXPOSED PAD (BOTTOM VIEW)1.00 0.85 12 MAX 0.80 MAX 0.65 TYP 0.50 9 8 5 4 BSC 1.50 REF 0.25 MIN 0.80 SEATING PLANE 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2 Figure 23.16-Lead Lead Frame Chip Scale Package LFCSP_VQ 3 mm 3 mm B
44、ody,Very Thin Quad(CP-16-1)Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Ordering Quantity Branding ADA4304-2ACPZ-RL1 ADA4304-2ACPZ-R71 ADA4304-2ACPZ-R21 40C to+85C 40C to+85C 40C to+85C 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ CP-16-1 CP-16-1 CP-16-1 5,000 1,500 250 H0Z H0Z H0Z 1 Z=RoHS Compliant Part.