《数字设计课件第6章组合逻辑设计实践.ppt》由会员分享，可在线阅读，更多相关《数字设计课件第6章组合逻辑设计实践.ppt（104页珍藏版）》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。
1、Chapter 6 Combinational Logic Design PracticesMSI building blocks are the important element of combinational circuits.2/17/20231本章重点n具备一定功能的通用组合逻辑电路的设计方法及实例n掌握常用的MSI的使用方法及功能扩展n掌握译码器、MUX实现组合逻辑功能的方法n能分析、设计由MSI构建的电路2/17/20232chapter 66.1 Documentation Standard1.Signal Names and Active LevelsMost signal
2、s(signal name)have active level.active high active lowNaming convention surffix“_L”attaching to signal name represent active low level.Like,EN_L、READY_L In logic relation,EN_L=EN，READY_L=READY。2/17/20233chapter 62.Active levels for pinsENEN_LDinstartDoutflgstart_LDinDoutflg_LInversion bubbleActive l
3、owENENDinstartDoutflgstartDinDoutflgActive hign2/17/20234chapter 6Exp2：EN=1(active high),data can be transferredEN=0(active low),data can be transferredENCLKEN_LCLK2/17/20235chapter 63.bubble-to-bubble logic designMake the logic circuit easier to understand.Exp：Not matchNot matchABSELDATAABASELDATAm
4、atchmatch2/17/20236chapter 66.3 Combinational PLDs1.Programmable logic arrays(PLA)two level“ANDOR”device.Can be programmed to realize any sum-of-products logic expression.An nm PLA with p product terms:ninputs moutputs pproduct terms2/17/20237chapter 643 with 6 product termsAND arrayOR arrayOR array
5、2/17/20238chapter 62/17/20239chapter 62.Programmable Array Logic DevicesFixed OR array，programmable AND arrayBidirectional input/output pins，熔丝型，熔丝型PAL16L8，Output enable2/17/202310chapter 63.Generic Array Logic Devices（GAL）an innovation of the PAL;can be erased and reprogrammed;2/17/202311chapter 66
6、.4 DecodernAn important type of combinational circuit.input code wordenable inputOutput code word decodeer1-to-1mapping1-out-of-m codenmn-bitm-bit2/17/202312chapter 61、bianry decodersninput code：n-bitnoutput code：2n-bit 2-4 decoder（2-22）I1I0Y3Y2Y1Y0truth table：？：？Yi：？：？I1I0Y3 Y2 Y1 Y0000001010010100
7、100111000Yi=miY0=I1I0Y1=I1I0Y2=I1I0Y3=I1I02-4decoderOne input combination chooses an output port.2/17/202313chapter 6n2-4 decoder with enable inputYi=EN miENI1I0Y3Y2Y1Y0000001000001101001011001001111000I1I0Y3Y2Y1Y0EN2-4 decoder2/17/202314chapter 6（2）74139,dual 2-4 decoderInput code：B（MSB）A（LSB）Also
8、be called address input.Output code：Y3_LY0_LEN 2/17/202315chapter 6（3）74138,3-8 decoderuEnable inputEN=G1G2A_LG2B_LuInput code：C（MSB）、）、B、AuOutput code：Y0_L Y7_LuYi_L=（ENmi）Y0_LY1_LY2_LY3_L Y4_L Y5_L Y6_L Y7_LG1G2A_LG2B_LEN2/17/202316chapter 6ENmsblsb2/17/202317chapter 62、realizing combinational cir
9、cuits with decodernreview：canonical sumnDecoder output：Yi_L=(ENmi)when EN=1，Yi_L=mi=Mi add an NAND gate to the decoders output.Exp:(1)F=ABAB（0、3）F=AB+ABEnable asserted2/17/202318chapter 6（2）if a 3-bit number XYZ is odd number，then ODD output 1，else output 0.realize the function with decoder and gate
10、s.solution：F=？F=XYZ（1，3，5，7）2/17/202319chapter 6（3）F=XYZ（0、1、5）解：解：2/17/202320chapter 63.Cascading binary decodersnHow to construct a 4-16、5-32 decoder？use multiple 2-4 or 3-8 decoders to cascade.nPS.：confirm the number of decoders according to the input and output bits.only one chip works in each d
11、ecoding operation.2/17/202321chapter 6Exp：a 4-16 decoderInputs:4-bit N3、N2、N1、N0。Outputs:16-bit DEC15_LDEC0_LNeed 2 3-8 decoders.Use the MSB of the inputs as chip-select bit.000000010111100010011111N3 N2 N1 N0N3 N2 N1 N02/17/202322chapter 6Chip selecting2/17/202323chapter 6nExp：4-bit prime-number de
12、tector.Realizing it with 74138 and some gates.N3N2N1N0F2/17/202324chapter 64、7-segment decoderClassify of 7-seg displayer：in materials:LED（发光二极管）（发光二极管）LCD（液晶）（液晶）In working mode:common-cathode(共阴极共阴极)common-anode(共阳极共阳极)afbcegddpabcdedpfggndgnd2/17/202325chapter 67-segment decoder transform the inp
13、ut BCD code to 7-segment displaying code.devices：7446A、74LS47（驱动共阳）（驱动共阳）74LS48、74LS49（驱动共阴）（驱动共阴）00001001 are useful input codes.10101111 are unused BCD code.2/17/202326chapter 674LS492/17/202327chapter 65、BCD decoder（二（二十进制译码器）十进制译码器）Inputs:BCDY0Y9BCD decoderOutput:1-out-of 10 code74HC422/17/20232
14、8chapter 65.5 Encoder1、binary encoder inputs:1-out-of-2n codeI0I1Im(m=2n-1)output:n-bitY0Y1Yn-1binary encoder2/17/202329chapter 68-3 encoderinputoutputI7I6I5I4I3I2I1I0Y2Y1Y01000000011101000000110001000001010001000010000001000011000001000100000001000100000001000In/out:active high2/17/202330chapter 6Y
15、0=I1+I3+I5+I7Y1=I2+I3+I6+I7Y2=I4+I5+I6+I7Each input port has its corresponding output code.2/17/202331chapter 62、Priority Encoderif multiple inputs are asserted,how to deal with?solution：assign priority to each input from high to low.let I7 highest priority and decrease from I6 down to I0 A2,A1,A0en
16、code output IDLEwhen no input is asserted,IDLE=12/17/202332chapter 6inputoutputI7I6I5I4I3I2I1I0A2A1A0IDLE111100111000011010000110000000101100000010100000000100100000000100000000000000012/17/202333chapter 6Logic expressions for priority encoderH7=I7H6=I6I7H5=I5I6I7H0=I0I1I2I3I4I5I6I7A2=H4+H5+H6+H7A1=
17、H2+H3+H6+H7A0=H1+H3+H5+H7IDLE=(I0+I1+I2+I3+I4+I5+I6+I7)=I0I1I2I3I4I5I6I7Expressions for each asserted input in the truth table of priority encoderOutput code expressions 2/17/202334chapter 63、74148 Priority EncoderEI_L：Enable Input.I7_LI0_L：encode input，I7_L has highest priority.A2_LA0_L：encode outp
18、utGS_L：GS_L=0 when one or more of the request inputs are asserted.EO_L：enable output,EO_L=0 when all of the request inputs are negative and EI_L=0.高高低低优优先先级级2/17/202335chapter 6n74148真值表真值表2/17/202336chapter 64、cascading priority encoderproblem：how to construct 16-4、32-5 priority encoder？Connecting
19、multiple 8-3 endoder.nnote：make sure the needed number of chips according to the inputs.need to redesign the output circuit that could produce the correct encoding output.2/17/202337chapter 6n16-4 priority encoder:use two 74148 U1、U2，(1)U1:input E15_LE8_L;U2:input E7_LE0_L;E15_L is the highest prior
20、ity,(2)output:A3_LA0_L，active low;(3)When one or more inputs is asserted，GS0_L=0；and A3_LA0_L=1111.2/17/202338chapter 616-4 priority encoderU174HC148A09A110A211GS14D34D45D56D23D12D78D67EI12EO13U274HC148A09A110A211GS14D34D45D56D23D12D01D78D67EI12EO13U3A74HC08U3B74HC08U3C74HC08U3D74HC08D01EN15_LEN14_L
21、EN13_LEN12_LEN11_LEN10_LEN9_LEN8_LEN7_LEN6_LEN5_LEN4_LEN3_LEN2_LEN1_LEN0_LD0_LD1_LD2_LD3_LGS_L2/17/202339chapter 6n思考：若需要编码输出、思考：若需要编码输出、GS0为高电平有效，如何为高电平有效，如何修改电路输出结构？修改电路输出结构？nP.413 figure 6-49 shows the 32-5 priority encoders strcture,.2/17/202340chapter 66.6 Three-state Devices1、three-state buffe
22、rs2/17/202341chapter 6EN_LEN_LA AOUTOUTENENEN_LEN_LA AA AOUT_LOUT_LOUT_LOUT_LEnable means:the buffer output normal logic 0、1 when EN is asserted；the buffer output Hi-Z when EN is negated.2/17/202342chapter 6lApplication data返回时序返回时序返回时序返回时序 address of data source2/17/202343chapter 6lIssues in applic
23、ation TPLZ、TPHZ：time that takes from normal logic into Hi-Z;TPZL、TPZH：time that takes from Hi-Z into normal logic;generally，TPLZ、TPHZ TPZL、TPZH But to confirm the correction in application,a control logic is adopted.2/17/202344chapter 674138的的相关相关引脚引脚信号信号查看电路查看电路查看电路查看电路 截止时间截止时间（停滞时间）（停滞时间）2/17/202
24、345chapter 6课堂练习课堂练习n试设计一个电路，当控制信号试设计一个电路，当控制信号M=1时，电路为时，电路为“判一致判一致”电路，即当三个输入变量取值全部相同电路，即当三个输入变量取值全部相同时输入为时输入为1；当控制信号；当控制信号M=0时，电路为时，电路为“多数表多数表决决”电路，即输出等于输入变量中占多数的取值。电路，即输出等于输入变量中占多数的取值。请写出最简表达式。（注：至少要写出卡诺图，请写出最简表达式。（注：至少要写出卡诺图，三变量为三变量为X、Y、Z）2/17/202346chapter 66.7 Multiplexer2-to-1 MUXABSELYY=SELA+
25、SELBS=0，Y=AS=1，Y=BABS=0Y=AABS=1Y=BLogic circuit2/17/202347chapter 6又称数据选择器，简称又称数据选择器，简称MUXOutput:enableselect n data source data output n2s mj：SELj minterm1、基本结构：、基本结构：2/17/202348chapter 6Let b=1,D0D1DjDn-1SELENY Y2/17/202349chapter 6Exp:4-to-1 MUXABCDS1S001101234outputCS0S1output00A01B10C11D2/17/20
26、2350chapter 62、MSI MUX（1）8-to-1 MUX，74151EN_LaddressY_LY2/17/202351chapter 6返回返回2/17/202352chapter 6G_LG_L S S（2）4-bit,2 input MUX，741572/17/202353chapter 6（3）2 bit,4 input MUX，74 153inputoutput1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C11010
27、02C2101102C311001G_L2G_L2/17/202354chapter 63、Expanding MUXsExp1：use 74151 to realize a 16-to-1 MUX,some gates can be used if necessary.Chips needed：according to the 16 inputs,2 74151 chips.output：combine two chips outputs into one output.2/17/202355chapter 6The MSB(A3)of input act as the chip-selec
28、t bit.2/17/202356chapter 64、用、用MUX实现组合逻辑函数的标准和实现组合逻辑函数的标准和 multiple input,1 bit MUX,the output：when EN is asserted：the canonical sum form.74151的内部电路的内部电路mj:minterm of the select(address)inputs.2/17/202359chapter 6MUX的数据输入端与真值表的每行输出对应，的数据输入端与真值表的每行输出对应，MUX的地址选择端作为最小项产生器，即的地址选择端作为最小项产生器，即 真值表：真值表：输出值输
29、出值输入变量输入变量 MUX：数据输入端数据输入端地址端地址端Exp1：a circuit output 1 when its 3-bit input can be divided by 3.construct the circuit by using 74151.So：F=XYZ（？）（？）and circuit？按最小项编号顺序按最小项编号顺序变量与选择端对应变量与选择端对应2/17/202360chapter 6n例例1的电路的电路XYZFU1W6D04D13D22D31D415D514D613D712S011S29S110Y5G7VCCGNDR12/17/202361chapter 6
30、例例2：若例：若例1中输入数为中输入数为4位二进制数，如何实现？位二进制数，如何实现？解解1：用：用16输入，输入，1位的位的MUX来实现，选用来实现，选用74150。F=WXYZ（0，3，6，9，12，15）解解2：仍选用：仍选用74151，先对所求函数的卡诺图做降，先对所求函数的卡诺图做降维处理。维处理。l预备知识：预备知识：卡诺图的降维卡诺图的降维 用一个用一个n变量的卡诺图来处理变量的卡诺图来处理m变量的函数变量的函数（nB)F(A=B)F(AB=ABFABFABFA=BFAB=(A1B1)+(A1=B1)(A0B0)=A1B1+(AB+AB)(A1B1)FA=B=(A1=B1)(A0
31、=B0)FAB=(A1B1)+(A1=B1)(A0BFA=BFABA1B11A1=B1A0B01A1=B1A0=B01Pseudo-logic2/17/202391chapter 64.Standard MSI magnitude comparator7485:4-bituMagnitude input:A3.0,B3.0uCascading input：ALBI、AEBI、AGBI，which are used to expanding comparator.uoutput：ALBO、AEBO、AGBOAGBO=(AB)+(A=B)AGBIAEBO=(A=B)AEBIALBO=(ABFA=B
32、FABFA=BFABX11.8Y11.8X7.4Y7.4X3.0Y3.02/17/202394chapter 6Class exerciseABCDFDAADCDCABJudge whether the following circuit has static hazard or not,if static hazard exist,please point it and eliminate by using K-map.Then write the hazardless minimal sum.2/17/202395chapter 66.10 Adders、Subtractors and A
33、LUnUsed to do binary addition and subtraction1.Half adders and full adders（1）half addersXYHSCO0000011010101101half sum：HS=X Ycarry-out：CO=XYXYHSCO2/17/202396chapter 6（2）full addersCINXYSCO0000000110010100110110010101011100111111sum：S=X Y CINcarry：CO=XY+CINX+CINY2/17/202397chapter 62、ripple addersnUs
34、e 1-bit full adder as a module to construct n-bit ripple adder.XYCINCOSX0Y0S0C0C1XYCINCOSX1Y1S1XYCOSXn-1 Yn-1Sn-1C2Cn电路简单，扩展方便，但运算速度慢电路简单，扩展方便，但运算速度慢2/17/202398chapter 63、carry-lookahead addersParallel addersnissues：how to get the carry information early?nsolution：carry-lookahead（1）definition：carry
35、generating variable：gi=xiyi carry propagating variable：pi=xi+yi the Ci+1 carry-out：Ci+1=gi+piCi2/17/202399chapter 6Ci+1=gi+pi(gi-1+pi-1(g0+p0C0)C0=0，Ci is relative to addends only and just three level delay,which to reduce the computation time.（2 2）structureuSi=Xi Yi CiuCi+1=gi+piCi先行进先行进先行进先行进位逻辑位逻
36、辑位逻辑位逻辑SiXiXi-1X0YiYi-1Y0CiC0两级与或式两级与或式2/17/2023100chapter 6（3）MSI adders74283，4-bit carry-lookahead adders加法器的级联（加法器的级联（P.482图图6-89）2/17/2023101chapter 64、subtractornFull subtractorD=X Y BINBO=BINY+BINX+XYBINXYDBO0000000111010100110010011101011100011111XYBODBIN2/17/2023102chapter 6nIn algorithm,subtraction can be operated by using addition.X-Y=X+(Y)2s=X+(Y)1s+1nSo circuit can be manipulated：D=X Y BIN BO=(BINX+BINY+XY)DBINBOsubtractor2/17/2023103chapter 65、MSI arithmetic and logic unitsnperform a number of different arithmetic and logical operations.ALUABFSELMCINCOGPA=B2/17/2023104chapter 6