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1、University of Science and Technology of ChinaPLDPLD与数字系统设计与数字系统设计(2)(2)中国科学技术大学电子科学与技术系中国科学技术大学电子科学与技术系主讲教师：主讲教师：李李 辉辉1University of Science and Technology of ChinaWhat is FPGA?FPGAs are programmable devices that can be directly configured by the end user without the use of an integrated circuit fab
2、rication facility.They offer the designer the benefits of custom hardware,eliminating high development costs and manufacturing time.2University of Science and Technology of ChinaWhat is FPGA?They were first introduced in 1985 by Xilinx.Since then,many different FPGAs have been developed by number of
3、 companies such as AT&T,Actel,Altera,Motorola,QuickLogic,and Crosspoint Solutions.3University of Science and Technology of ChinaWhat is FPGA?Figure shows a conceptual diagram of a typical FPGA.4University of Science and Technology of ChinaWhat is FPGA?All Xilinx FPGAs contain the same basic resource
4、sSlices(grouped into CLBs)Contain combinatorial logic and register resourcesIOBsInterface between the FPGA and the outside worldProgrammable interconnect Other resourcesMemoryMultipliersGlobal clock buffersBoundary scan logic5University of Science and Technology of China1.3.2Spartan FPGA CMOS+SRAM T
5、echnology6University of Science and Technology of ChinaSRAM7University of Science and Technology of China8University of Science and Technology of ChinaStructure9University of Science and Technology of ChinaLUT10University of Science and Technology of ChinaCLB11University of Science and Technology of
6、 ChinaI/OB12University of Science and Technology of China13University of Science and Technology of China14University of Science and Technology of China1.3.3 Spartan-II 15University of Science and Technology of ChinaSpartan-II Structure 16University of Science and Technology of ChinaCLB Resources17Un
7、iversity of Science and Technology of ChinaCLB Resources18University of Science and Technology of ChinaCLB Resources19University of Science and Technology of ChinaCLB Resources20University of Science and Technology of ChinaCLB Resources21University of Science and Technology of ChinaCLB Resources(1)2
8、2University of Science and Technology of ChinaCLB Resourcesxc2s15-6-vq100Cell Usage:#BELS(A Basic Element):3#LUT4 :1#MUXF5 :1#VCC :1#FlipFlops/Latches :1#FDCE :123University of Science and Technology of ChinaCLB ResourcesThe FDCE is an asynchronously cleared,enabled D-type flip-flop.24University of
9、Science and Technology of ChinaCLB Resources(2)25University of Science and Technology of ChinaCLB Resourcesxc2s15-6-vq100Cell Usage:#BELS:3#LUT4 :1#MUXF5 :1#VCC :1#FlipFlops/Latches :1#FDRE :126University of Science and Technology of ChinaCLB ResourcesFDRE is a D-type flip-flop with data(D),clock en
10、able(CE),and synchronous reset(R)inputs and data output(Q).27University of Science and Technology of ChinaCLB Resources(3)28University of Science and Technology of ChinaCLB Resourcesxc2s15-6-vq100Cell Usage:#BELS:1#LUT4 :1#FlipFlops/Latches :1#FDSE :129University of Science and Technology of ChinaCL
11、B ResourcesFDRSE is a single D-type flip-flop with synchronous reset(CLR),synchronous set(PRE),and clock enable(CE)inputs and data output(Q).30University of Science and Technology of ChinaProgrammable I/O Standards31University of Science and Technology of ChinaProgrammable I/O Standards32University
12、of Science and Technology of ChinaProgrammable I/O Standards33University of Science and Technology of ChinaProgrammable I/O Standards34University of Science and Technology of ChinaProgrammable I/O Standards寄存器驻留在I/O单元35University of Science and Technology of ChinaProgrammable I/O Standards36Universi
13、ty of Science and Technology of ChinaProgrammable I/O Standards37University of Science and Technology of ChinaProgrammable I/O Standards Each bank has a input reference voltage(VREF).Shared among all I/Os in the bank.All I/O types in a bank must use the same VREF.All VREF pins in a bank must be tied
14、 together.Inputs not requiring a VREF fit in the bank.LVTTL,LVCMOS,LVPECL,LVDS,PCI.VREF pins in a bank available as additional I/O if no I/O in that bank requires a VREF.38University of Science and Technology of ChinaProgrammable I/O Standards Each bank has a single source voltage(VCCO).Shared among
15、 all I/Os in that bank.All I/O types in a bank must use the same VCCO.All VCCO pins in a bank must be tied together.39University of Science and Technology of ChinaProgrammable I/O Standards40University of Science and Technology of ChinaDDL 41University of Science and Technology of ChinaDDL42Universi
16、ty of Science and Technology of ChinaDDL43University of Science and Technology of ChinaSpartan-3/3E Family44University of Science and Technology of ChinaVirtex-4 LX Family45University of Science and Technology of ChinaVirtex-4 FX Family46University of Science and Technology of ChinaVirtex-4 SX Family47University of Science and Technology of ChinaEND48