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1、东南大学计算结构POC报告Computer Organization and ArchitectureCOURSE DESIGNNAME STUDENT NUMBER COURSEComputer Organization and Architecture Course DesignPROJECTA Parallel Output Controller Basing On Verilog HDLSOFTWARE PLATFORM ISE 14。1DATEMAR.17。20141. Purpose（1) To design and simulate a parallel output contr
2、oller (POC) which acts an interface between system bus and printer.(2) The use of ISE software for design and simulation.2。 Tasks(1) POC is one of the most common I/O modules， namely the parallel output controller。 It plays the role of an interface between the computer system bus and the peripheral
3、（such as a printer or other output devices）。 Figure 1 Printer ConnectionFigure shows the connecting of a printer to the system bus through the POC. (2） The communication between POC and the printer is controlled by a “handshake” protocol illustrated in Figure 。 Figure 2 The handshake-timing diagram
4、between POC and the printerThe handshaking process is described as follows: When the printer is ready to receive a character， it holds RDY=1.The POC must then hold a character at PD (parallel data） port and produce a pulse at the terminal TR （transfer request)。 The printer will change RDY to 0, take
5、 the character at PD and hold the RDY at 0 until the character has been printed (e。g。 5 or 10ms）, then set RDY=1 again when it is ready to receive the next character。 (Suppose the printer has only a one character “buffer” register， so that each character must be printed before the next character is
6、sent）。(3) The buffer register BR is used to hold a character that has been sent via the system bus while that the character is being transferred to the printer. The status register SR is used for two control functions： SR7serves as a ready flag for system bus transfers to BR （like the printer RDY si
7、gnal for transfers from POC to the printer）, and SR0 is used to enable or disable interrupt requests from POC。 If SR0=1， then POC will interrupt when it is ready to receive a character (i.e。, when SR7=1）。 If SR0=0， then POC will not interrupt。 The other bits of SR are not used and empty。(4) The tran
8、sfer of a character to POC via the system bus proceeds as follows。In polling mode, SR0 is always 0。The processor selects SR by accessing the relative address, then reads SR register， if SR7=1, the processor selects BR and writes a character into BR， then processor clears SR7 to indicate that the new
9、 character has been written into BR and not printed yet。 When POC detects that SR7 is set to 0, POC then proceeds to start the handshaking operations with the printer. After sending character to printer, POC sets the SR7 to 1, which indicates POC is ready to receive another character from the proces
10、sor. The transfer cycle can now repeat。 During the handshaking operations between POC and printer, the processor continues to fetch and execute instructions。 If it happens to read SR， it will find SR7=0 and hence will not attempt to send another character to the POC.In interrupt mode, SR0 is always
11、1。After sending character to printer, POC sets the SR7 to 1， since SR0=1， the interrupt request signal (IRQ） is set to 0， which indicate an effective interrupt signal to the processor. When the processor detects the effective IRQ signal， the processor directly selects BR and writes a character into
12、BR， and then the processor sets the SR7 to 0， which indicates that the new character has been written into BR and not printed yet. When POC detects that SR7 is set to 0, POC then proceeds to start the handshaking operations with the printer。 After sending character to printer, POC sets the SR7 to 1,
13、 which indicates POC is ready to receive another character from the processor。 The transfer cycle can now repeat. During the handshaking operations between POC and printer， the processor does not try to access POC until it receives the interrupt request signal.3。 The overall connection expressed in
14、the top module formFigure 3 The overall connection expressed in the top module formIn order to be easy to debug, some inside signals and registers are set as output signals。 In fact, we just only need clk, clk2， reset, cs and PD to be outside signals。Signals or registersFunctionclkClock of CPU and P
15、OCclk2Clock of PrinterresetReset when reset=0cscs=0:polling mode; cs=1:interrupt modePDData to be printedTable 1 The explication of the outside signals4。 Design description of the simulation input waveforms As is shown in table 1，4 simulation input signals are needed.（1)clk Clock of CPU and POC。(2）c
16、lk2 Clock of Printer, faster than clk。（3)reset Reset when reset=0.（4）cs cs=0:polling mode； cs=1:interrupt mode。5. Simulation results（1) In polling mode, cs=0， SR0 is always 0.（2） In interrupt mode， cs=1， SR0 is always 1.6。 Conclusions and DiscussionsPOC, parallel output controller， plays a role as a
17、n interface between CPU and the printer. As is shown above, the two simulation waves reveal that this design meets the requirements。 In my design， all the codes are my original works。 I have written the module Processor to help completing simulation， which need more codes and debugging to cooperate
18、with the work of POC。 Even there is already a schematic for the module Printer in the teaching material, I still have to do more work to finish this module because the software I use is ISE whose devices is different from those of Quartus II。The procedure of design helps me understand the working pr
19、inciple of interface. In the third term of Grade 2 did we learn something about computer interface in the course Microcomputer。 And the course COA has referred to it, too。 Here I use what I have learned to design this program and achieve a lot.In this program, I use the EDA software ISE and Verilog
20、hardware language to design those three modules and Isim， which is a module of ISE， and VHDL language for simulation。 As a result， I become more familiar with the use of hardware description language。Appendix-CPU-module POC_CPU( output RW, output ADDR, output 7：0 POCDin， input reset， input CLK, inpu
21、t 7：0 POCDout, input IRQ ); reg ADDR； reg 7：0 POCDin； reg RW； reg t1; reg t2; reg 7:0 n； /t为标记 always（posedge CLK） begin if（reset=0) begin t1=0;t2=0;n=8b00000000;RW=0;ADDR=0;POCDin=8b00000000；end else if（IRQ=0t2=0）/中断方式SR0=1，收到中断请求信号； begin ADDR=1； RW=1； POCDin=8b00000101+n; t2=1; end else if(t2=1）
22、begin ADDR=0; RW=1; POCDin=8b00000001； t2=0; n=n+1; end else if（RW=1&POCDin=8b00000001)begin RW=0; end else/查询方式 begin /ADDR=0;RW=0; if（RW=0&POCDout=8b10000000&t1=0)/查询方式SR0=0,SR7=1； begin ADDR=1; RW=1; POCDin=8b00000101+n; t1=1; end if（POCDout=8b10000000t1=1）/查询方式SR0=0，已完成数据传递,将把SR7置为0; begin ADDR=
23、0； RW=1; POCDin=8b00000000; t1=0；n=n+1； end if（RW=1&POCDin=8b00000000）begin RW=0； end end endendmodule-POC-module POC_POC( input ADDR, input 7:0 Din, input RW, input CLK, input reset, input cs， output IRQ, output TR, output 7:0 Dout, output 7：0 PD, output 7:0 SR， output 7：0 BR, input RDY ）； reg IRQ；
24、 reg TR; reg 7:0 Dout; reg 7：0 PD； reg 7：0 BR； reg 7:0 SR； always（posedge CLK） begin if(reset=0） begin IRQ=1;TR=0;Dout=8b00000000；PD=8b00000000；BR=8b00000000；SR=8b00000000;end else if（cs=0）/查询方式 begin if(ADDR=0&RW=0）/读SR到CPU begin if（SR7=0&RDY=1&TR=0) begin PD=BR； TR=1; Dout=SR; end else if(TR=1) be
25、gin TR=0;SR7=1；Dout=SR; end else begin Dout=SR； end end if（ADDR=0RW=1）/写SR BR写入新数据后SR7被置为0 begin SR=Din； end /if(ADDR=1&RW=0）/读BR begin Dout=BR; end*/ if(ADDR=1&RW=1)/写BR begin if（SR7=0&RDY=1&TR=0） beginBR=Din； PD=BR; TR=1;Dout=8b00000000； end else if(TR=1） begin TR=0;SR7=1；BR=Din；Dout=8b00000000; e
26、nd else begin BR=Din；Dout=8b00000000； end end end else if（cs=1）/中断方式 begin if(SR0=0）begin SR=8b00000001； end else if(ADDR=0&RW=0) /读SR begin if（SR7=0&RDY=1&TR=0） begin PD=BR； TR=1; IRQ=1;Dout=SR； end else if（TR=1) begin TR=0；IRQ=0;SR7=1;Dout=SR; end else begin Dout=SR；IRQ=1; end end else if(ADDR=0&R
27、W=1) /写SR BR写入新数据后SR7被置为0 begin SR=Din； end /*if(ADDR=1&RW=0） /读BR begin Dout=BR； end*/ else if（ADDR=1&RW=1) /写BR 此时SR7不可能为0 begin if(SR7=0&RDY=1TR=0) beginBR=Din; PD=BR； TR=1； IRQ=1;Dout=8b00000001; end else if（TR=1) begin TR=0；IRQ=0；SR7=1；BR=Din；Dout=8b00000001; end/else if（IRQ=0) begin IRQ=1; end else begin BR=Din；IRQ=1；Dout=8b00000001; end end end endendmodule-Printer-