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1、1简单数字电路设计简单数字电路设计2设计验证与仿真设计验证与仿真qVerilog HDL不不仅仅提提供供描描述述设设计计的的能能力力，而而且且提提供供对对激激励励、控制、存储响应和设计验证的建模能力。控制、存储响应和设计验证的建模能力。q激激励励和和控控制制可可用用初初始始化化语语句句产产生生。验验证证运运行行过过程程中中的的响响应应可可以作为以作为“变化时保存变化时保存”或作为选通的数据存储。或作为选通的数据存储。q最最后后，设设计计验验证证可可以以通通过过在在初初始始化化语语句句中中写写入入相相应应的的语语句句自自动与期望的响应值比较完成。动与期望的响应值比较完成。q要要测测试试一一个个设
2、设计计块块是是否否正正确确，就就要要用用Verilog再再写写一一个个测测试试模模块。这个测试模块应包括以下三个方面的内容：块。这个测试模块应包括以下三个方面的内容：测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中要调用到设计块，只有这样才能对它进行测试；测试模块中应包含测试的激励信号源；测试模块中应包含测试的激励信号源；测试模块能够实施对输出信号的检测，并报告检测结果。测试模块能够实施对输出信号的检测，并报告检测结果。3Simulating/Validating HDLThe sad truth10%design,90%validationIf you do it right
3、you will spend 9X more time testing/validating a design than designing it.DesignUnder Test(verilog)StimulusGeneration(verilog)OutputMonitoringSelf Checking(verilog)filefileVerilog test bench shellTestbenchs are written in verilog as well.Testbench verilog is not describing hardware and can be though
4、t of as more of a program.4Testbench Example(contrived but valid)module test_and;integer file,i,code;reg a,b,expect,clock;wire out;parameter cycle=20;and#4 a0(out,a,b);/Circuit under testinitial begin:file_block clock=0;file=$fopen(compare.txt,“r”);for(i=0;i 4;i=i+1)begin (posedge clock)/Read stimul
5、us on rising clock code=$fscanf(file,%b%b%bn,a,b,expect);#(cycle-1)/Compare just before end of cycle if(expect!=out)$strobe(%d%b%b%b%b,$time,a,b,expect,out);end/for$fclose(file);$stop;end/initialalways#(cycle/2)clock=clock;/Clock generatorendmodule5组合逻辑设计组合逻辑设计q组合逻辑电路组合逻辑电路 可可以以有有若若个个输输入入变变量量和和若若干干个
6、个输输出出变变量量，其其每每个个输输出出变变量量是是其其输输入入的的逻逻辑辑函函数数，其其每每个个时时刻刻的的输输出出变变量量的的状状态态仅仅与与当当时时的的输输入入变变量量的的状状态态有有关关，与与本本输输出出的的原原来来状状态态及及输输入入的的原原状状态态无无关关，也也就就是是输输入入状状态态的的变变化化立立即即反映在输出状态的变化反映在输出状态的变化。q逻辑电路的各种运算可以用布尔代数来描述逻辑电路的各种运算可以用布尔代数来描述q狄摩根定律狄摩根定律利利用用狄狄摩摩根根（DeMorgan）定定律律可可以以将将积积之之和和形形式式的的电电路路转转换换为为和和之之积形式的电路，或反之。积形式
7、的电路，或反之。6q组合逻辑的三种通用表示方法组合逻辑的三种通用表示方法结构化（即门级）原理图结构化（即门级）原理图真值表真值表布尔方程式布尔方程式q实例：半加器实例：半加器二进制输入二进制输入和输出和输出进位输出进位输出basco00000110101011017Combinational CircuitsComponent InstantiationsCircuit A connection of modules Also known as structure A circuit is a second way to describe amodule vs.using an always
8、procedure,as earlierInstance An occurrence of a module in acircuit May be multiple instances of a module e.g.,Cars modules:tires,engine,windows,etc.,with 4 tire instances,1 engine instance,6 window instances,etc.8Combinational CircuitsModule Instantiations9Combinational CircuitsModule Instantiations
9、10Combinational CircuitsModule Instantiations11Combinational Circuit StructureSimulatingg the CircuitSame testbench format for BeltWarnmodule as for earlier And2 module12Combinational Circuit StructureSimulatingg the Circuit13Combinational Circuit StructureSimulatingg the Circuittimescale 1 ns/1 nsm
10、odule Testbench();reg K_s,P_s,S_s;wire W_s;BeltWarn CompToTest(K_s,P_s,S_s,W_s);initial beginMore on testbenches Note that a single module instantiationstatement used reg and wire declarations(K_s,P_s,S_s,W_s)used because procedurecannot access instantiated modules=0;S_sP_s=1;P_s=1;P_s=1;=0;S_s=0;S_
11、s=0;S_s=1;K_s=0;P_s#10 K_s=0;#10 K_s=1;#10 K_s=1;endendmoduleports directly Inputs declared as regs so can assignvalues(which are held betweenassignments)Note module instantiation statementand procedure can both appear in onemodule14Combinational Behavior to Structure15Combinational Behavior to Stru
12、ctureAlways Procedures with Assignment Statements16Combinational Behavior to StructureProcedures with Assignment StatementsProcedural assignment statement Assigns value to variable Right side may be expression ofoperatorstimescale 1 ns/1 nsmodule BeltWarn(K,P,S,W);input K,P,S;output W;reg W;Built-in
13、 bit operators include&AND|OR NOTXORXNORalways(K,P,S)beginW=K&P&S;endendmodule Q:Create an always procedure tocompute:F=CH+CHAnswer 1:always(C,H)beginF=(C&H)|(C&H);endAnswer 2:always(C,H)beginF=C H;end17Combinational Behavior to StructureProcedures with Assignment StatementsProcedure may have multip
14、leassignment statementstimescale 1 ns/1 nsmodule TwoOutputEx(A,B,C,F,G);input A,B,C;output FF,G;reg F,G;always(A,B,C)beginF=(B&B)|C;G=(A&B)|(B&C);endendmodule18Combinational Behavior to StructureProcedures with If-Else StatementsProcess may use if-else statements(a.k.a.conditional statements)if(expr
15、ession)If expression is true(evaluates tononzero value),executecorresponding statement(s)If false(evaluates to 0),executeelsess statement(else part isoptional)Example shows use of operator=timescale 1 ns/1 nsmodule BeltWarn(K,P,S,W);input K,P,S;output W;reg W;always(K,P,S)beginif(K&P&S)=1)W=1;elseW=
16、0;logical equality,returns true/false(actually,returns 1 or 0)endendmodule True is nonzero value,false is zero19Combinational Behavior to StructureProcedures with If-Else StatementsMore than two possibilities Handled by stringing if-elsestatements together Known as if-else-if constructExample:4x1 mu
17、x behaviortimescale 1 ns/1 nsmodule Mux4(I3,I2,I1,I0,S1,S0,D);input I3,I2,I1,I0;input S1,S0;output D;SupposeS1S0change to01 Suppose S1S0 change to 01 ifs expression is false elses statement executes,which is an if statementwhose expression is truereg D;always(I3,I2,I1,I0,S1,S0)beginif(S1=0&S0=0)D=I0
18、;else if(S1=0&S0=1)D=I1;else if(S1=1&S0=0)D=I2;elseD=I3;Note:The following indentation shows ifstatement nesting,but is unconventional:if(S1=0&S0=0)endendmoduleD=I0;elseif(S1=0&S0=1)D=I1;else&logical AND&:bit AND(operands are bits,returns bit)&:logical AND(operands are true/falseif(S1=1&S0=0)D=I2;el
19、seD=I3;values,returns true/false)20Combinational Behavior to StructureProcedures with If-Else Statements21Combinational Behavior to Structure22Combinational Behavior to StructureCommon Pitfall Missing Inputs from Event Control Expression23Combinational Behavior to StructureCommon Pitfall Missing Inp
20、uts from Event Control ExpressionVerilog provides mechanism to help avoidthis pitfall *implicit event control expression Automatically adds all nets and variablesthat are read by the controlled statement orstatement group Thus,*in example is equivalent to(S1,S0,I0,I1,I2,I3)timescale 1 ns/1 nsmodule
21、Mux4(I3,I2,I1,I0,S1,S0,D);input I3,I2,I1,I0;input S1,S0;output D;reg D;(*)also equivalentalways*beginif(S1=0&S0=0)D=I0;else if(S1=0&S0=1)D=I1;else if(S1=1&S0=0)D=I2;elseD=I3;endendmodule24Combinational Behavior to StructureCommon Pitfall Output not Assigned on Every Pass25Combinational Behavior to S
22、tructureCommon Pitfall Output not Assigned on Every PassSame pitfall often occurs due to not considering allpossible input combinationsif(I1=0&I0=0)beginD3=0;D2=0;D1=00;D0=11;endelse if(I1=0&I0=1)beginD3=0;D2=0;D1=1;D0=0;endelse if(I1=1&I0=0)beginD3=0;D2=1;D1=0;D0=0;Last else missing,so not allendinput combinations are covered(i.e.,I1I0=11 not covered)