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1、-第 1 页单片机外文文献和中文翻译-第 2 页Validation and Testing of Design Hardening for SingleEvent Effects Using the 8051 MicrocontrollerAbstractWith the dearth of dedicated radiation hardened foundries,new and novel techniquesare being developed for hardening designs using non-dedicated foundry services.Inthis pap
2、er,we will discuss the implications of validating these methods for the singleevent effects(SEE)in the space environment.Topics include the types of tests thatare required and the design coverage(i.e.,design libraries:do they need validatingfor each application?).Finally,an 8051 microcontroller core
3、 from NASA Institute ofAdvanced Microelectronics(IAE)CMOS Ultra Low Power Radiation Tolerant(CULPRiT)design is evaluated for SEE mitigative techniques against two commercial8051 devices.Index TermsSingle Event Effects,Hardened-By-Design,microcontroller,radiation effects.I.INTRODUCTIONNASA constantly
4、 strives to provide the best capture of science while operating in aspace radiation environment using a minimum of resources 1,2.With a relativelylimited selection of radiation-hardened microelectronic devices that are often two ormore generations of performance behind commercial state-ofthe-art tec
5、hnologies,NASAs performance of this task is quite challenging.One method of alleviating this isby the use of commercial foundry alternatives with no or minimally invasive designtechniques for hardening.This is often called hardened-by-design(HBD).Buildingcustom-type HBD devices using design librarie
6、s and automated design tools mayprovide NASA the solution it needs to meet stringent science performancespecifications in a timely,cost-effective,and reliable manner.However,one question still exists:traditional radiation-hardened devices have lotand/or wafer radiation qualification tests performed;
7、what types of tests are requiredfor HBD validation?II.TESTING HBD DEVICES CONSIDERATIONSTest methodologies in the United States exist to qualify individual devices throughstandards and organizations such as ASTM,JEDEC,and MIL-STD-883.Typically,TID(Co-60)and SEE(heavy ion and/or proton)are required f
8、or device validation.Sowhat is unique to HBD devices?As opposed to a“regular”commercial-off-the-shelf(COTS)device or applicationspecific integrated circuit(ASIC)where no hardening has been performed,one needsto determine how validated is the design library as opposed to determining the devicehardnes
9、s.That is,by using test chips,can we“qualify”a future device using the samelibrary?Consider if Vendor A has designed a new HBD library portable to foundries B and C.A test chip is designed,tested,and deemed acceptable.Nine months later a NASAflight project enters the mix by designing a new device us
10、ing Vendor As library.Doesthis device require complete radiation qualification testing?To answer this,other-第 3 页questions must be asked.How complete was the test chip?Was there sufficient statistical coverage of alllibrary elements to validate each cell?If the new NASA design uses a partially orins
11、ufficiently characterized portion of the design library,full testing might be required.Of course,if part of the HBD was relying on inherent radiation hardness of a process,some of the tests(like SEL in the earlier example)may be waived.Other considerations include speed of operation and operating vo
12、ltage.Forexample,if the test chip was tested statically for SEE at a power supply voltage of3.3V,is the data applicable to a 100 MHz operating frequency at 2.5V?Dynamicconsiderations(i.e.,nonstatic operation)include the propagated effects of SingleEvent Transients(SETs).These can be a greater concer
13、n at higher frequencies.The point of the considerations is that the design library must be known,thecoverage used during testing is known,the test application must be thoroughlyunderstood and the characteristics of the foundry must be known.If all these areapplicable or have been validated by the te
14、st chip,then no testing may be necessary.A task within NASAs Electronic Parts and Packaging(NEPP)Program wasperformed to explore these types of considerations.III.HBD TECHNOLOGY EVALUATION USING THE 8051 MICROCONTROLLERWith their increasing capabilities and lower power consumption,microcontrollersar
15、e increasingly being used in NASA and DOD system designs.There are existingNASA and DoD programs that are doing technology development to provide HBD.Microcontrollers are one such vehicle that is being investigated to quantify theradiation hardness improvement.Examples of these programs are the 8051
16、microcontroller being developed by Mission Research Corporation(MRC)and theIAE(the focus of this study).As these HBD technologies become available,validation of the technology,in the natural space radiation environment,for NASAsuse in spaceflight systems is required.The 8051 microcontroller is an in
17、dustry standard architecture that has broadacceptance,wide-ranging applications and development tools available.There arenumerous commercial vendors that supply this controller or have it integrated intosome type of system-on-a-chip structure.Both MRC and IAE chose this device todemonstrate two dist
18、inctly different technologies for hardening.The MRC example ofthis is to use temporal latches that require specific timing to ensure that single eventeffects are minimized.The IAE technology uses ultra low power,and layout andarchitecture HBD design rules to achieve their results.These are fundament
19、allydifferent than the approach by Aeroflex-United Technologies Microelectronics Center(UTMC),the commercial vendor of a radiation hardened 8051,that built their 8051microcontroller using radiation hardened processes.This broad range of technologywithin one device structure makes the 8051an ideal ve
20、hicle for performing thistechnology evaluation.The objective of this work is the technology evaluation of the CULPRiT process 3from IAE.The process has been baselined against two other processes,thestandard 8051 commercial device from Intel and a version using state-of-the-artprocessing from Dallas
21、Semiconductor.By performing this side-by-side comparison,-第 4 页the cost benefit,performance,and reliability trade study can be done.In the performance of the technology evaluation,this task developed hardware andsoftware for testing microcontrollers.A thorough process was done to optimize thetest pr
22、ocess to obtain as complete an evaluation as possible.This included takingadvantage of the available hardware and writing software that exercised themicrocontroller such that all substructures of the processor were evaluated.Thisprocess is also leading to a more complete understanding of how to test
23、 complexstructures,such as microcontrollers,and how to more efficiently test these structuresin the future.IV.TEST DEVICESThree devices were used in this test evaluation.The first is the NASA CULPRiTdevice,which is the primary device to be evaluated.The other two devices are twoversions of a commerc
24、ial 8051,manufactured by Intel and Dallas Semiconductor,respectively.The Intel devices are the ROMless,CMOS version of the classic 8052 MCS-51microcontroller.They are rated for operation at+5V,over a temperature range of 0 to70 C and at a clock speeds of 3.5 MHz to 24 MHz.They are manufactured in In
25、telsP629.0 CHMOS III-E process.The Dallas Semiconductor devices are similar in that they are ROMless 8052microcontrollers,but they are enhanced in various ways.They are rated for operationfrom 4.25 to 5.5 Volts over 0 to 70 C at clock speeds up to 25 MHz.They have asecond full serial port built in,s
26、even additional interrupts,a watchdog timer,a powerfail reset,dual data pointers and variable speed peripheral access.In addition,thecore is redesigned so that the machine cycle is shortened for most instructions,resulting in an effective processing ability that is roughly 2.5 times greater(faster)t
27、han the standard 8052 device.None of these features,other than those inherent inthe device operation,were utilized in order to maximize the similarity between theDallas and Intel test codes.The CULPRiT technology device is a version of the MSC-51 family compatibleC8051 HDL core licensed from the Ult
28、ra Low Power(ULP)process foundry.TheCULPRiT technology C8051 device is designed to operate at a supply voltage of 500mV and includes an on-chip input/output signal level-shifting interface withconventional higher voltage parts.The CULPRiT C8051 device requires two separatesupply voltages;the 500 mV
29、and the desired interface voltage.The CULPRiT C8051is ROMless and is intended to be instruction set compatible with the MSC-51 family.V.TEST HARDWAREThe 8051 Device Under Test(DUT)was tested as a component of a functionalcomputer.Aside from DUT itself,the other componentsof the DUT computer were rem
30、oved from the immediate area of the irradiation beam.A small card(one per DUT package type)with a unique hard-wired identifier bytecontained the DUT,its crystal,and bypass capacitors(and voltage level shifters forthe CULPRiT DUTs).This DUT Board was connected to the Main Board by a short60-conductor
31、 ribbon cable.The Main Board had all other components required tocomplete the DUT Computer,including some which nominally are not necessary in-第 5 页some designs(such as external RAM,external ROM and address latch).The DUT Computer and the Test Control Computer were connected via a serialcable and co
32、mmunications were established between the two by the Controller(thatruns custom designed serial interface software).This Controller software allowed forcommanding of the DUT,downloading DUT Code to the DUT,and real-time errorcollection from the DUT during and postirradiation.A 1 Hz signal source pro
33、videdan external watchdog timing signal to the DUT,whose watchdog output wasmonitored via an oscilloscope.The power supply was monitored to provide indicationof latchup.VI.TEST SOFTWAREThe 8051 test software concept is straightforward.It was designed to be a modularseries of small test programs each
34、 exercising a specific part of the DUT.Since eachtest was stand alone,they were loaded independently of each other for execution onthe DUT.This ensured that only the desired portion of the 8051 DUT was exercisedduring the test and helped pinpoint location of errors that occur during testing.All test
35、programs resided on the controller PC until loaded via the serial interface to the DUTcomputer.In this way,individual tests could have been modified at any time withoutthe necessity of burning PROMs.Additional tests could have also been developedand added without impacting the overall test design.Th
36、e only permanent code,whichwas resident on the DUT,was the boot code and serial code loader routines thatestablished communications between the controller PC and the DUT.All test programs implemented:An external Universal Asynchronous Receive and Transmit device(UART)fortransmission of error informa
37、tion and communication to controller computer.An external real-time clock for data error tag.A watchdog routine designed to provide visual verification of 8051 health andrestart test code if necessary.A foul-up routine to reset program counter if it wanders out of code space.An external telemetry da
38、ta storage memory to provide backup of data in the eventof an interruption in data transmission.The brief description of each of the software tests used is given below.It should benoted that for each test,the returned telemetry(including time tag)was sent to boththe test controller and the telemetry
39、 memory,giving the highest reliability that all datais captured.Interrupt This test used 4 of 6 available interrupt vectors(Serial,External,Timer0Overflow,and Timer1 Overflow)to trigger routines that sequentially modified a valuein the accumulator which was periodically compared to a known value.Une
40、xpectedvalues were transmitted with register information.Logic This test performed a series of logic and math computations and providedthree types of error identifications:1)addition/subtraction,2)logic and 3)multiplication/division.All miscompares of computations and expected results weretransmitte
41、d with other relevant register information.Memory This test loaded internal data memory at locations D:0 x20 through D:0 xff(or D:0 x20 through D:0 x080 for the CULPRiT DUT),indirectly,with an 0 x55 pattern.-第 6 页Compares were performed continuously and miscompares were corrected while errorinformat
42、ion and register values were transmitted.Program Counter-The program counter was used to continuously fetch constantsat various offsets in the code.Constants were compared with known values andmiscompares were transmitted along with relevant register information.Registers This test loaded each of fo
43、ur(0,1,2,3)banks of general-purposeregisters with either 0 xAA(for banks 0 and 2)or 0 x55(for banks 1 and 3).The patternwas alternated in order to test the Program Status Word(PSW)special functionregister,which controls general-purpose register bank selection.General-purposeregister banks were then
44、compared with their expected values.All miscompares werecorrected and error information was transmitted.Special Function Registers(SFR)This test used learned static values of 12 out 21available SFRs and then constantly compared the learned value with the current one.Miscompares were reloaded with le
45、arned value and error information was transmitted.Stack This test performed arithmetic by pushing and popping operands on thestack.Unexpected results were attributed to errors on the stack or to the stack pointeritself and were transmitted with relevant register information.VII.TEST METHODOLOGYThe D
46、UT Computer booted by executing the instruction code located at address0 x0000.Initially,the device at this location was an EPROM previously loaded withBoot/Serial Loader code.This code initialized the DUT Computer and interfacethrough a serial connection to the controlling computer,the Test Control
47、ler.TheDUT Computer downloaded Test Code and put it into Program Code RAM(located onthe Main Board of the DUT Computer).It then activated a circuit which simultaneouslyperformed two functions:held the DUT reset line active for some time(10 ms);and,remapped the Test Code residing in the Program Code
48、RAM to locate it to address0 x0000(the EPROM will no longer be accessible in the DUT Computers memoryspace).Upon awaking from the reset,the DUT computer again booted by executingthe instruction code at address 0 x0000,except this time that code was not be theBoot/Serial Loader code but the Test Code
49、.The Test Control Computer always retained the ability to force the reset/remapfunction,regardless of the DUT Computers functionality.Thus,if the test ran withouta Single Event Functional Interrupt(SEFI)either the DUT Computer itself or the TestController could have terminated the test and allowed t
50、he post-test functions to beexecuted.If a SEFI occurred,the Test Controller forced a reboot into Boot/SerialLoader code and then executed the post-test functions.During any test of the DUT,the DUT exercised a portion of its functionality(e.g.,Register operations or Internal RAM check,or Timer operat