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1、 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSemiconductor Semiconductor Manufacturing TechnologyManufacturing TechnologyMichael Quirk&Julian Serda Michael Quirk&Julian Serda October 2001 by Prentice HallOctober 2001 by Prentice HallChapter 17Chapter 1
2、7 Doping ProcessesDoping Processes 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaObjectivesAfter studying the material in this chapter,you will be able to:1.Explain the purpose and applications for doping in wafer fabrication.2.Discuss the principles and
3、 process of dopant diffusion.3.Provide an overview of ion implantation,including its advantages and disadvantages.4.Discuss the importance of dose and range in ion implant.5.List and describe the five major subsystems for an ion implanter.6.Explain annealing and channeling in ion implantation.7.Desc
4、ribe different applications of ion implantation.2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaCommon Dopants Used in Semiconductor ManufacturingTable 17.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaCMOS St
5、ructure with Doped Regionsn-channel Transistorp-channel TransistorLI oxidep epitaxial layerp+silicon substrateSTISTISTIn+p+p-welln-wellp+pp+pp+n+nn+nn+ABCEFDGHKLIJMMNOn+nn+p+pp+Figure 17.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaCommon Dopant Proce
6、sses in CMOS FabricationTable 17.2 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaIon Implant in Process FlowUsed with permission from Lance Kinney,AMDImplantDiffusionTest/SortEtchPolishPhotoCompleted waferUnpatterned waferWafer startThin FilmsWafer fabri
7、cation(front-end)Hard mask(oxide or nitride)Anneal after implantPhotoresist maskFigure 17.2 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaDoped Region in a Silicon WaferOxideOxidep+Silicon substrateDopant gasNDiffused regionFigure 17.3 2001 by Prentice H
8、allSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaDiffusionDiffusion PrinciplesThree StepsPredepositionDrive-inActivationDopant MovementSolid SolubilityLateral DiffusionDiffusion ProcessWafer CleaningDopant Sources 2001 by Prentice HallSemiconductor Manufacturing Technologyby
9、 Michael Quirk and Julian SerdaDopant Diffusion in SiliconDisplaced silicon atom in interstitial siteSiSiSiSiSiSiSiSiSic)Mechanical interstitial displacementSiSiSiSiSiSiSiSiSia)Silicon lattice structureb)Substitutional diffusionSiSiSiSiSiSiSiSiVacancyDopantd)Interstitial diffusionSiSiSiSiSiSiSiSiSiD
10、opant in interstitial siteFigure 17.4 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSolid Solubility Limits in Silicon at 1100CTable 17.3 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaDiffusion ProcessEight S
11、teps for Successful Diffusion:1.Run qualification test to ensure the tool meets production quality criteria.2.Verify wafer properties with a lot control system.3.Download the process recipe with the desired diffusion parameters.4.Set up the furnace,including a temperature profile.5.Clean the wafers
12、and dip in HF to remove native oxide.6.Perform predeposition:load wafers into the deposition furnace and diffuse the dopant.7.Perform drive-in:increase furnace temperature to drive-in and activate the dopant bonds,then unload the wafers.8.Measure,evaluate and record junction depth and sheet resistiv
13、ity.2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaTypical Dopant Sources for DiffusionSEMATECH“Diffusion Processes,”Furnace Processes and Related Topics,(Austin,TX:SEMATECH,1994),P.7.Table 17.4 2001 by Prentice HallSemiconductor Manufacturing Technologyb
14、y Michael Quirk and Julian SerdaIon ImplantationOverviewControlling Dopant ConcentrationAdvantages of Ion ImplantDisadvantages of Ion ImplantIon Implant ParametersDoseRange 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaControlling Dopant Concentration an
15、d Deptha)Low dopant concentration(n,p)and shallow junction(xj)MaskMaskSilicon substratexjLow energyLow doseFast scan speedBeam scanDopant ionsIon implanterb)High dopant concentration(n+,p+)and deep junction(xj)Beam scanHigh energyHigh doseSlow scan speedMaskMaskSilicon substratexjIon implanterFigure
16、 17.5 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaGeneral Schematic of an Ion ImplanterIon sourceAnalyzing magnetAcceleration columnIon beamPlasmaProcess chamberExtraction assemblyScanning diskFigure 17.6 2001 by Prentice HallSemiconductor Manufacturin
17、g Technologyby Michael Quirk and Julian SerdaIon ImplanterPhotograph courtesy of Varian Semiconductor,VIISion 80 Source/Terminal sidePhoto 17.1 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaAdvantages of Ion Implantation(from Table 17.5)1.Precise Control
18、 of Dopant Concentration2.Good Dopant Uniformity3.Good Control of Dopant Penetration Depth4.Produces a Pure Beam of Ions5.Low Temperature Processing6.Ability to Implant Dopants Through Films7.No Solid Solubility LimitTable 17.5 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Qu
19、irk and Julian SerdaClasses of ImplantersTable 17.6 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaRange and Projected Range of Dopant IonIncident ion beamSilicon substrateStopping point for a single ionRpDRp dopant distributionFigure 17.7 2001 by Prentic
20、e HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaProjected Range ChartImplantation Energy(keV)Projected Range,Rp(mm)101001,0000.010.11.0BPAsSbImplanting into SiliconFigure 17.8 Redrawn from B.El-Kareh,Fundamentals of Semiconductor Processing Technologies,(Boston:Kluwer,19
21、95),p.388 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaEnergy Loss of an Implanted Dopant AtomSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiSiX-raysElectronic collisionAtomic collisionDisplaced Si atomEnergetic dopant ionSilicon crystal latticeFigure 17
22、.9 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaCrystal Damage Due to Light and Heavy IonsLight ion impactHeavy ion impactFigure 17.10 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaIon ImplantersIon SourceEx
23、traction and Ion AnalyzerAcceleration ColumnScanning SystemProcess ChamberAnnealingChannelingParticles 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSchematic of Ion Source ChamberUsed with permission from Applied Materials Technology,Precision Implanter
24、 9500 Figure 17.11 Extraction assemblySource chamberTurbo pumpIon source insulatorBernas ion source assemblyArc chamberExtraction electrodeExtraction assemblyIon beam 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSchematic of Bernas Ion SourceFront Plate
25、ApertureArc ChamberFilamentElectron repellerGas inlets5 VElectron reflectorAnode+100 VArc chamberVapor nozzleOvenGas feed tubeDI cooling water inletDopant gas inletUsed with permission from Applied Materials Technology,Precision Implanter 9500 Figure 17.12 2001 by Prentice HallSemiconductor Manufact
26、uring Technologyby Michael Quirk and Julian SerdaInteraction of ion Source and Extraction AssembliesUsed with permission from Applied Materials Technology,Precision Implanter 9500+-NS N S120 VArcExtraction AssemblyIon Source60 kVExtraction2.5 kVSuppressionSource magnet supply5VFilamentTo PA+Ion beam
27、Terminal reference(PA voltage)Suppression electrodeGrounded electrodeArc chamberFigure 17.13 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaAnalyzing MagnetGraphiteIon sourceAnalyzing magnetIon beamExtraction assemblyLighter ionsHeavy ionsNeutralsFigure 1
28、7.14 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaIon Implanter Analyzing MagnetPhotograph courtesy of Varian Semiconductor,VIISion 80 analyzer sidePhoto 17.2 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaAc
29、celeration Column100 MW100 MW100 MW100 MW100 MW0 kV+100 kV+80 kV+20 kV+40 kV+60 kV+100 kVIon beamIon beamTo process chamberElectrodeFrom analyzing magnetFigure 17.15 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaDose Versus Energy MapProximity getteringP
30、resent applicationsEvolving applicationsPoly dopingSource/drainDamageengineeringBuried layersRetrogradewellsTriple wellsVt adjustChannel and drain engineering0.1110100100010,0001016101110121013101410151017Energy(keV)Dose(atoms/cm2)Used with permission from Varian Semiconductor EquipmentFigure 17.16
31、2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaLinear Accelerator for High-Energy ImplantersSourceAtomic mass analysis magnetLinear acceleratorFinal energy analysis magnetScan diskWaferFigure 17.17 2001 by Prentice HallSemiconductor Manufacturing Technolo
32、gyby Michael Quirk and Julian SerdaSpace Charge Neutralization+Cross section of beamwith space charge neutralization+Cross section of beam blow-upDopant ionSecondary electronFigure 17.18 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaNeutral Beam TrapSour
33、ceAnalyzing MagnetAcceleratorNeutral beam trapFocussing anodeY-axisdeflectionX-axisdeflectionNeutral beam pathWaferIon beamGrounded collector plateUsed with permission from Varian Semiconductor Equipment Figure 17.19 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Jul
34、ian SerdaElectrostatic Ion Beam Scanning of Wafer+Ion beamY-axisdeflectionX-axisdeflectionWaferTwistTiltHigh frequency X-axis deflectionLow frequency Y-axis deflectionFigure 17.20 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaImplant ShadowingResista)Mec
35、hanical scanning with no tiltIon beamb)Electrostatic scanning with normal tiltResistIon beamFigure 17.21 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaMechanical Scanning of Implanted WafersOuter scan radiusInner scan radiusImplant area(calculated)Spillo
36、ver cupRotationIon beamUsed with permission from Varian Semiconductor Equipment,VIISion 80 Ion Implanter Figure 17.22 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaElectron Shower for Wafer Charging ControlAdapted from Eaton NV10 ion implanter,circa 1983
37、+Ion beam-Biased apertureElectron gunSecondary electron targetSecondary electrons+Ion-electronrecombinationWaferFigure 17.23 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPlasma Flood to Control Wafer Charging-BiasedapertureIon beamNeutralized atomsWafer
38、 scan directionCurrent(dose)monitorPlasma electron flood chamberArgon gas inletElectron emissionChamber wall+SNSN+ArArArFigure 17.24 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaEnd Station for Ion ImplanterPhotograph provided courtesy of International
39、SEMATECHPhoto 17.3 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaWafer Handler for an Implant Process ChamberUsed with permission from Varian Semiconductor Equipment,VIISion 200 Ion ImplanterVIISionEnd StationProcess ChamberTerminal SubsystemSource Subsy
40、stemImplant SubsystemOperator interfaceWafer cassette loadlocksWafer handlerScan diskVideo monitorWallFigure 17.25 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFaraday Cup Beam Current MeasurementRedraawn from S.Ghandhi,VLSI Fabricaton Principles:Silico
41、n and Gallium Arsenide,2d ed.,(New York:Wiley,1994),p.417Scanning disk with wafersScanning directionFaraday cupSuppressor apertureCurrent integratorSampling slit in diskIon beamFigure 17.26 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaAnnealing of Silic
42、on CrystalRepaired Si lattice structure and activated dopant-silicon bondsb)Si lattice after annealinga)Damaged Si lattice during implantIon BeamFigure 17.27 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSilicon Lattice Viewed Along AxisUsed with permiss
43、ion from Edgard Torres DesignsFigure 17.28 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaIon Entrance Angle and ChannelingUsed with permission from Edgard Torres DesignsFigure 17.29 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Qu
44、irk and Julian SerdaImplantation Damage from Particulate ContaminationMaskMaskSilicon SubstrateBeam scanIon implanterParticle creates a void in implanted areaFigure 17.30 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaIon Implant Trends in Process Integra
45、tionExamples of Different Implant ProcessesDeep buried layersRetrograde wellsPunchthrough stoppersThreshold voltage adjustmentLightly doped drain(LDD)Source/drain implantsPolysilicon gateTrench capacitorUltra-shallow junctionsSilicon on Insulator(SOI)2001 by Prentice HallSemiconductor Manufacturing
46、Technologyby Michael Quirk and Julian SerdaBuried Implanted LayerFigure 17.31 n-wellp-wellp-Epi layerp+Silicon substratep+Buried layerRetrograde wells 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaRetrograde Welln-wellp-wellp+Buried layerp+Silicon substr
47、aten-type dopantp-type dopantp+n+Figure 17.32 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPunchthrough Stopn-wellp-wellp+Buried layerp+Silicon substraten-type dopantp-type dopantp+p+n+n+Figure 17.33 2001 by Prentice HallSemiconductor Manufacturing Tech
48、nologyby Michael Quirk and Julian SerdaImplant for Threshold Voltage Adjustmentn-wellp-wellp+Buried layerp+Silicon substraten-type dopantp-type dopantp+p+pn+n+nFigure 17.34 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaSource-Drain Formations+-+-n-wellp-
49、wellp+Buried layerp+Silicon substratep+S/D implantn+S/D implantSpacer oxideDrainSourceDrainSourceb)p+and n+Source/drain implants(performed in two separate operations)+-n-wellp-wellp+Buried layerp+Silicon substratep-channel transistorp LDD implantn-channel transistorn LDD implantDrain SourceDrain Sou
50、rcePoly gatea)p and n lightly-doped drain implants(performed in two separate operations)Figure 17.35 2001 by Prentice HallSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaDopant Implant on Vertical Sidewalls of Trench Capacitorn+dopantn+p+Tilted implantTrench for forming capaci