各种MII类型接口详解.pdf

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1、各种 MII 类型接口详解简介MII 是英文 Medium Independent Interface的缩写，翻译成中文是“介质独立接口”，该接口一般应用于以太网硬件平台的MAC 层和 PHY 层之间，MII 接口的类型有很多，常用的有MII、RMII、SMII、SSMII、SSSMII、GMII、RGMII、SGMII、TBI、RTBI、XGMII、XAUI、XLAUI等。下面对它们进行一一介绍。MII 接口：TXD(Transmit Data)3:0：数据发送信号，共4 根信号线；RXD(Receive Data)3:0：数据接收信号，共4 根信号线；TX_ER(Transmit Erro

2、r)：发送数据错误提示信号，同步于TX_CLK，高电平有效，表示TX_ER 有效期内传输的数据无效。对于10Mbps 速率下，TX_ER 不起作用；RX_ER(Receive Error)：接收数据错误提示信号，同步于RX_CLK，高电平有效，表示RX_ER 有效期内传输的数据无效。对于10Mbps 速率下，RX_ER 不起作用；TX_EN(Transmit Enable)：发送使能信号，只有在TX_EN 有效期内传的数据才有效；RX_DV(Reveive Data Valid)：接收数据有效信号，作用类型于发送通道的TX_EN；TX_CLK：发送参考时钟，100Mbps 速率下，时钟频率为2

3、5MHz，10Mbps 速率下，时钟频率为 2.5MHz。注意，TX_CLK时钟的 方向 是从 PHY 侧指向MAC 侧 的，因此此 时钟是 由PHY 提供的。RX_CLK：接收数据参考时钟，100Mbps 速率下，时钟频率为25MHz，10Mbps 速率下，时钟频率为 2.5MHz。RX_CLK 也 是由 PHY 侧提供 的。CRS：Carrier Sense，载波侦测 信号，不 需要 同步于参考时钟，只要 有数据传输，CRS 就有效，另外，CRS 只有 PHY 在半双工模式 下有效；COL：Collision Detectd，冲突检测 信号，不 需要 同步于参考时钟，只有PHY 在半双工模

4、式下有效。MII 接口一共有16 根线。各种 MII 类型接口详解RMII接口：RMII 即 Reduced MII，是 MII 的简化板，连线数 量由 MII 的 16 根 减少 为 8 根。TXD1:0：数据发送信号线，数据位宽 为 2，是 MII 接口的一 半；RXD1:0：数据接收信号线，数据位宽 为 2，是 MII 接口的一 半；TX_EN(Transmit Enable)：数据发送使能信号，与 MII 接口中的该信号线功能一 样；RX_ER(Receive Error)：数据接收错误提示信号，与 MII 接口中的该信号线功能一 样；CLK_REF：是 由外部 时钟 源提供 的 50

5、MHz 参考时钟，与 MII 接口不同，MII 接口中的接收时钟和发送时钟是分开 的，而且都 是由 PHY 芯片 提供给 MAC 芯片 的。这里需要注意的是，由于数据接收时钟是由外部晶振 提供而 不是 由载波 信号提 取的，所以在 PHY 层芯片 内的数据接收 部分需要设计 一个 FIFO，用 来协调两个 不同的时钟,在发送接收的数据时提供缓冲。PHY 层芯片 的发送 部分则 不需要 FIFO，它 直接将接收 到的数据发送 到 MAC 就可 以了。CRS_DV：此信号是 由 MII 接口中的RX_DV 和 CRS 两个 信号 合并而 成。当介质不 空闲 时，CRS_DV 和 RE_CLK 相异

6、 步的 方式给出。当 CRS 比 RX_DV 早结束 时(即载波消失而队列中还有数据 要传输时)，就会出现 CRS_DV 在半位元组 的边界 以 25MHz/2.5MHz的频率在0、1 之间的 来回 切换。因此，MAC 能够从 CRS_DV 中精确 的 恢复 出 RX_DV 和 CRS。在 100Mbps 速率时，TX/RX 每个时钟 周期采样一个数据；在10Mbps 速率时，TX/RX 每隔10 个周期采样一 个数据，因而 TX/RX数据 需要 在数据线 上保留 10 个 周期，相当 于一 个数据发送 10 次。当 PHY 层芯片 收到有效的 载波 信号 后，CRS_DV 信号 变为有效，此

7、时如果 FIFO 中还没有数据，则它会发送 出全 0 的数据 给 MAC，然后 当 FIFO 中填入 有效的数据 帧，数据 帧的开头是“101010-”交叉 的前导码，当 数据中 出现“01”的比特时，代表正式数据传输 开始，MAC芯片检测到这 一变化，从而开 始接收数据。当外部载波 信号 消失 后，CRS_DV 会变为无效，但如果 FIFO 中还有数据 要发送时，CRS_DV在下一 周期又会变为有效，然后再 无效 再有效，直到 FIFO 中数据发送 完为止。在接收 过程中如果 出现 无效的 载波 信号 或者 无效的数据 编码，则 RX_ER 会变 为有效，表示 物理 层芯片接收 出错。SMI

8、I 接口：文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y

9、4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J

10、6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y

11、4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J

12、6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y

13、4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J

14、6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9各种 MII 类型接口详解SMII 即 Serial MII，串行 MII 的意思，跟 RMII 相比，连线进一步 减少到 4根；TXD：发送数据信号，位宽 为 1；RXD：接收数据信号，位宽 为 1；SYNC：收发数据同步信号，每 10 个时钟 周期置 1 次高电平，指示同步。CLK_REF：所 有 端口共用的一 个参考时钟，频率为125MHz，

15、为 什么 100Mbps 速率 要用125MHz 时钟？因为在 每 8 位数据中 会插入 2 位控制 信号，请看 下面介绍。TXD/RXD以 10 比特为一 组，以 SYNC 为高电平 来指 示一 组数据的 开始，在 SYNC 变高后的 10 个时钟 周期内，TXD上依次 输出的数据是：TXD7:0、TX_EN、TX_ER，控制 信号的含义 与 MII 接口中的 相同；RXD 上依次 输出的数据是：RXD7:0、RX_DV、CRS，RXD7:0的含义 与 RX_DV 有关，当 RX_DV 为有效时(高电平)，RXD7:0 上传输的是 物理 层接收的数据。当 RX_DV 为无效时(低电平)，RX

16、D7:0 上传输的是 物理 层的 状态 信息数据。见 下表：当速率为 10Mbps 时，每一组数据 要重复 10 次，MAC/PHY芯片 每 10 个周期采样一次。MAC/PHY芯片 在接收 到数据 后 会进行 串/并转换。SSMII 接口：SSMII 即 Serial Sync MII，叫串 行同步接口，跟 SMII 接口很类 似，只是收发使用独立的参考时钟和同步时钟，不再像 SMII 那样收发共用参考时钟和同步时钟，传输 距离 比 SMII 更远。文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1

17、G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1

18、Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1

19、G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1

20、Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1

21、G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1

22、Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1

23、G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9各种 MII 类型接口详解SSSMII 接口：SSSMII 即 Source Sync Serial MII，叫源同步 串行 MII 接口，SSSMII 与 SSMII 的区别 在于参考时钟和同步时钟的方向，SSMII 的 TX/RX参考时钟和同步时钟都是由 PHY 芯片 提供的，而 SSSMII 的 TX 参考时钟和同步时钟是由 MAC 芯片提供的，RX 参考时钟和同步时钟是由 PHY 芯片提供的，所以顾名思义叫 源同步串行。GMII接口：文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9

24、ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V

25、3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9

26、ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V

27、3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9

28、ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V

29、3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9

30、ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9各种 MII 类型接口详解与 MII 接口 相比，GMII 的数据 宽度由 4 位变为 8 位，GMII 接口中的 控制 信号如 TX_ER、TX_EN、RX_ER、RX_DV、CRS 和 COL 的作用同MII 接口中的一 样，发 送 参 考 时 钟GTX_CLK和 接 收 参 考 时 钟RX_CLK的 频 率 均 为125MHz(1000Mbps/8=125MHz)。在这里 有一点需要 特别说明 下，那就是发送

31、参考时钟GTX_CLK，它和MII接口中的 TX_CLK 是不同的，MII 接口中的TX_CLK 是由 PHY 芯片 提供给 MAC芯片 的，而 GMII 接口中的GTX_CLK是由 MAC 芯片 提供给 PHY 芯片 的。两者方向 不一 样。在实际 应用中，绝大 多数 GMII 接口 都是兼容 MII 接口的，所以，一般的 GMII接口 都有两个发送参考时钟：TX_CLK和 GTX_CLK(两者的方向 是不一 样的，前面已经说过 了)，在用作MII 模式 时，使用TX_CLK和 8 根数据线中的4 根。RGMII接口：RGMII 即 Reduced GMII，是 RGMII 的简化 版本，将

32、接口信号线数 量从 24根减少到 14 根(COL/CRS 端 口状态指示信号，这里没有画出)，时钟频率 仍旧 为125MHz，TX/RX 数据 宽度从 8 为变为 4 位，为了保持 1000Mbps 的传输速率不变，RGMII接口在时钟的上升沿和下 降沿 都采样数据。在参考时钟的上升沿 发送 GMII接口中的TXD3:0/RXD3:0，在参考时钟的下降沿 发送 GMII 接口中的 TXD7:4/RXD7:4。RGMI 同时 也兼容 100Mbps 和 10Mbps 两种速率，此时参考时钟速率 分别为 25MHz 和 2.5MHz。TX_EN 信号线 上传送 TX_EN 和 TX_ER 两种信

33、息，在 TX_CLK的上升沿 发送 TX_EN，下 降沿 发送 TX_ER；同 样的，RX_DV 信号线 上也传送 RX_DV 和RX_ER 两种信息，在 RX_CLK 的上升沿 发送 RX_DV，下 降沿 发送 RX_ER。文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S

34、9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP

35、9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S

36、9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP

37、9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S

38、9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP

39、9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9各种 MII 类型接口详解SGMII接口：SGMII即 Serial GMII，串行 GMII，收发 各一对 差 分信号线，时钟频率6

40、25MHz，在时钟信号的上升沿 和下 降沿 均采 样，参考时钟RX_CLK 由 PHY 提供，是可选的，主要用于 MAC 侧没有时钟的 情况，一般 情况下，RX_CLK 不使用。收发 都可以从数据中 恢复 出时钟。在 TXD 发送的 串行数据中，每 8 比特数据 会插入 TX_EN/TX_ER 两比 特控制信息，同 样，在 RXD 接收数据中，每 8 比特数据 会插入 RX_DV/RX_ER 两比特控制 信息，所以总的数据速率为1.25Gbps=625Mbps*2.其实，大多数 MAC 芯片 的 SGMII 接口 都可 以配置成 SerDes接口(在物理上完全兼容，只需配置寄存器 即可)，直接

41、外接光模块，而不需要 PHY 层芯片，此时时钟速率 仍旧 是 625MHz，不 过此时跟 SGMII 接口不同，SGMII 接口速率 被提高 到 1.25Gbps 是因为插入 了控制 信息，而 SerDes端口速率 被提高是 因为进行了 8B/10B 变换，本来 8B/10B 变换 是 PHY 芯片 的工作，在 SerDes 接口中，因为外面不接 PHY 芯片，此时 8B/10B 变换 在 MAC 芯片 中完成了。8B/10B 变换的主要作用是 扰码，让信号中不 出现 过长的连“0”和连“1”情况，影响 时钟信 息的提取，关于 8B/10B 变换 知识，我后续会单独介绍。文档编码:CP9V3I

42、1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC

43、1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I

44、1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC

45、1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I

46、1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC

47、1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I

48、1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9各种 MII 类型接口详解TBI 接口：TBI 即 Ten Bit Interface 的 意思，接口数据 位宽由 GMII 接口的 8 位增加到 10位，其实，TBI 接口 跟 GMII 接口的 差别不是很 大，多 出来 的 2 位数据 主要是因为在 TBI 接口下，MAC 芯片 在将数据发 给 PHY 芯片 之前进行 了 8B/10B 变换(8B/10B 变换 本是在 PHY

49、 芯片 中完成的，前面已经说过 了)，另外，RX_CLK+/-是从接收数据中 恢复 出来 的半频时钟，频率为62.5MHz，RX_CLK+/-不是 差分信号，而是两个 独立的信号，两者之间有 180 度的相位 差，在这两个 时钟的 上升沿都采样数据。RX_CLK+/-也叫伪差 分信号。除掉 上面说到的之 外，剩下的信号都跟 GMII 接口中的 相同。大多数 芯片的 TBI 接口和 GMII 接口 兼容。在用作 TBI 接口时，CRS 和 COL一般不用。RTBI 接口：RTBI 即Reduced TBI，简化 版 TBI，接口数据位宽 为 5bit，时钟频率为125MHz，在时钟的 上升沿 和

50、下 降沿 都采样数据，同RGMII接口一 样，TX_EN文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1G4J6H7H9文档编码:CP9V3I1Z4Y4 HT1O2J6H4S9 ZC1