可编程逻辑器件实验手册.pdf

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1、 Exercise Manual for Quartus II Software Design Series:Foundation Software Requirements to complete all exercises Quartus II software version 11.1 Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 2 Exercise 1 Quartus II Software Design Series:Foundation Exerci

2、ses Copyright 2012 Altera Corporation 3 Exercise 1 Objectives:Create a project using the New Project Wizard Name the project Pick a device Note:In these exercises,youll create a brand new project and complete an existing design.Youll have the choice of creating the design using three different types

3、 of design entry:Verilog,VHDL,or as a Quartus II schematic.Where noted,be sure to only follow the instructions appropriate for your choice of design entry method.By the end of the class,youll have a final,optimized design,ready for programming into a Cyclone III FPGA device.Be sure to completely rea

4、d the instructions for each step and sub-step in this lab manual.Each step first summarizes what youll be doing in that step before providing complete instructions.Use the lines next to each step(_)to keep track of your progress or to check off completed steps in the exercises.If you have any questi

5、ons or problems,please ask the instructor for assistance.Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 4 Step 1:Create new project for use in the lab exercises _ 1.Unzip the lab project files.Double-click the executable file found in the.zip file you downlo

6、aded.In the WinZip dialog box,click Unzip to automatically extract the files in place to a new folder named C:altera_trnQuartus_II_Software_Design_Series_FoundationQIIF11_1_OLT.Close WinZip._ 2.Start the Quartus II software.In the Windows Start menu from the All Programs list,go to the Altera folder

7、 and then the Quartus II 11.1 folder.Click Quartus II 11.1 to start the program.There may also be a shortcut on the desktop._ 3.Start the New Project Wizard.You can open it from the Getting Started With Quartus II Software welcome dialog that appears.If youve closed this window,in the Tasks window o

8、n the left side of the Quartus II interface,expand the Start Project folder and double-click Open New Project Wizard.You can also select New Project Wizard from the File menu.The New Project Wizard appears.If the Introduction screen appears,read it and click Next._ 4.Complete the New Project Wizard

9、to create the project.Select one of the working directories shown in Table 1 depending on the type of design entry you want to use.Name the project pipemult and leave the top level entity name pipemult.Table 1.Settings for page 1 of New Project Wizard _ 5.Click Next to advance to page 2.working dire

10、ctory QIIF11_1_OLTEx1VHDL QIIF11_1_OLTEx1Verilog QIIF11_1_OLTEx1Schematic name of project pipemult top-level design entity pipemult Quartus II Software Design Series:Foundation Exercises Copyright 2012 Altera Corporation 5 _ 6.On page 2,click the browse button and select the top-level file pipemult(

11、.v,.vhd,or.bdf,depending on the design entry method you chose in#4).It should already be located in the project directory,if not,navigate to the project directory.After clicking Open,click Add to add the file to the project.Click Next.Note that this step isnt really necessary since the design file i

12、s already located in the project working directory.The new project would automatically include the design file as part of the project.Files or file directories(libraries)only need to be added on page 2 of the New Project Wizard if they are not located in the project directory.Adding the file to the

13、project removes the warning that the file has not been added._ 7.On page 3,select Cyclone III as the Family.In the Show in Available device list section,set Package to FBGA,Pin count to 256,and Speed grade to Fastest.This filters the list of available devices.Select the EP3C5F256C6 device from the A

14、vailable devices:window.Click Next.Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 6 _ 8.On page 4(above),you can specify third-party EDA tools you may be using.Since these exercises will be done entirely within the Quartus II software without any other tools

15、,click Next to skip this step._ 9.The summary screen appears as shown.Click Finish.The project is now created.Keep the project open as you continue through the exercises.There is no need to close the project.If you do close the project for some reason,be sure to select Open Project instead of just O

16、pen from the File menu(or Open Existing Project from the Tasks window).The Open command is used to simply open a single file instead of a project,preventing the ability to perform many project-based operations,such as compilation.Exercise Summary Created a project using the New Project Wizard Named

17、the project Picked a device END OF EXERCISE 1 Quartus II Software Design Series:Foundation Exercises Copyright 2012 Altera Corporation 7 Exercise 2 Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 8 Exercise 2 Objectives:Create a multiplier and RAM block using

18、 the MegaWizard Plug-in Manager to complete the design Create a HEX file to initialize the RAM block using the Memory Editor Analyze and elaborate the design to check for errors Pipelined Multiplier Design Figure 1 shows a schematic representation of the top-level design file you will be using today

19、.It consists of a multiplier and a RAM block.Data is fed to the multiplier from an external source and stored in the RAM block,which is also controlled externally.The data is then read out of the RAM block by a separate address control.Figure 1 Quartus II Software Design Series:Foundation Exercises

20、Copyright 2012 Altera Corporation 9 IMPORTANT NOTE:For exercises 2-6,you should either continue working in the Ex1 directory(preferred),or you can open a project(File menu or Tasks window Open Existing Project Select pipemult.qpf and click Open)found in one of the Ex#directories.The Ex#directories e

21、ach contain projects in the three versions(schematic,Verilog,VHDL)completed up to the beginning of that exercise in the exercise manual.The Solutions directory contains a Word document with the answers to questions asked in the exercises as well as the final project as it would be set up at the end

22、of exercise 6.Step 1:Build an 8x8 multiplier using the MegaWizard Plug-in Manager _ 1.Choose Tools MegaWizard Plug-In Manager or double-click MegaWizard Plug-In Manager in the Create Design folder of the Tasks window.In the window that appears,select Create a new custom megafunction variation.Click

23、Next._ 2.Select the megafunction to create.On page 2a(shown above),expand the Arithmetic folder and select LPM_MULT.22 _ 3.In the drop-down menu,make sure the Cyclone III device family is selected.The selection of a device family here lets the MegaWizard Plug-In Manager know what device resources ar

24、e available as the megafunction is created.You could change the device family if you wanted to create the same megafunction but for a different project that uses a different device.Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 10 _ 4.Choose VHDL or Verilog

25、HDL output depending on your choice of HDL and exercise directory.If you are using the Schematic exercise,choose either VHDL or Verilog._ 5.For the name of the output file,type mult.You can add this to the end of the directory path or erase the entire path to automatically place the generated megafu

26、nction files in the project directory._ 6.Click Next._ 7.On page 3(General),set the width of the dataa and datab buses to 8 bits if they are not already set.For the remaining settings in this window,use the defaults that appear.Click Next.Quartus II Software Design Series:Foundation Exercises Copyri

27、ght 2012 Altera Corporation 11 _ 8.On page 4(General 2),use all the default settings(i.e.datab input does NOT have a constant value,use unsigned multiplication,and select the default multiplier implementation).Click Next.Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Co

28、rporation 12 _ 9.On page 5(Pipelining),choose Yes,I want an output latency of 2 clock cycles.Click Next._ 10.You should now be on page 6(section 2 of the MegaWizard called EDA).This tab indicates the simulation model file needed to simulate LPM_MULT in an EDA simulation tool(e.g.ModelSim or some oth

29、er 3rd-party simulation tool).The lpm simulation model file should be indicated as shown above.You also have the option of generating a timing and resource estimation netlist for use by a 3rd-party synthesis tools.We are not using any third-party tools,so just click Next.Quartus II Software Design S

30、eries:Foundation Exercises Copyright 2012 Altera Corporation 13 _ 11.On page 7,using Table 2 below check the appropriate boxes depending on the Design Entry Method selected.Table 2.MegaWizard files to generate _ 12.Click Finish to create the megafunction.If a dialog box appears asking if you want to

31、 add the QIP file to the Quartus II project,click Yes.The multiplier is built.If for some reason your megafunction is incorrect or you forgot or missed a checkbox for generating all the required output files,open the MegaWizard Plug-In Manager again from the Tools menu or Tasks window.Select to edit

32、 an existing megafunction.Then select the main variation file for the megafunction(mult.v or mult.vhd),and go through the pages of the MegaWizard again(skip around with the tabs at the top)to fix your mistakes or generate the missing file(s).Click Finish to update the megafunction files.Step 2:Creat

33、e HEX file using the Memory Editor Design Entry Method Files to Enable in MegaWizard Plug-In VHDL mult_inst.vhd,&mult.cmp Verilog mult_inst.v&mult_bb.v Schematic mult_inst(.vhd or.v)&mult.bsf Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 14 _ 1.From the Tas

34、ks window,in the Create Design folder,double-click Create New Design File.(You may have to change the Tasks Flow to Full Design.)You could also go to the File menu and select New or click in the toolbar._ 2.In the New dialog box,expand the Memory Files category and select Hexadecimal(Intel-Format)Fi

35、le.(This hex file will be used to initialize a dual port RAM we will be creating in the next step)_ 3.Click OK._ 4.In the memory size dialog box,choose 32 as the number of words and 16 as the word size._ 5.Click OK.Quartus II Software Design Series:Foundation Exercises Copyright 2012 Altera Corporat

36、ion 15 The Memory Editor now displays your memory space.If your memory space is not displayed exactly as above,you can change the number of cells per row(View menu)to 16,the memory radix(View menu)to Hexadecimal,and the address radix to Decimal._ 6.Highlight all of the memory locations in your memor

37、y space.Right-click and select Custom Fill Cells._ 7.Use the Custom Fill Cells dialog box to enter your own values to initialize your memory.You can enter any values you want.Do one of the following:a.Repeating Sequence:Enter a series of numbers separated by commas or spaces to be repeated in memory

38、.b.Incrementing/Decrementing:Enter a start value and another value by which to increment or decrement the start value._ 8.Save the file as ram.hex in the project directory(you may have to navigate to the project directory again before you save).Close ram.hex.Exercises Quartus II Software Design Seri

39、es:Foundation Copyright 2012 Altera Corporation 16 Step 3:Create a 32x16 RAM using the MegaWizard Plug-In Manager _ 1.Open the MegaWizard Plug-In Manager again(Tools or Tasks window MegaWizard Plug-In Manager).Select to Create a new custom megafunction variation,and click Next._ 2.Select the megafun

40、ction to create.On page 2a(shown below),do the following:a.Expand the Memory Compiler folder and select RAM:2-PORT.b.As before,choose the Cyclone IV E device family and VHDL or Verilog HDL.c.For the name of the output file,enter ram._ 3.Click Next._ 4.On page 3,select One read port and one write por

41、t for the Dualport RAM mode.Select memory size by words.Click Next Quartus II Software Design Series:Foundation Exercises Copyright 2012 Altera Corporation 17 _ 5.On page 4(Widths/Blk Type),set the width of the data_a bus to 16 and the number of 16-bit words to 32.Select the Memory block type to Aut

42、o and Max depth to Auto._ 6.Click Next twice._ 7.On page 7(Regs/Clkens/Aclrs),disable the option to register the Read output port(s)q.Accept the remaining default settings,and click Next 2 times.Exercises Quartus II Software Design Series:Foundation Copyright 2012 Altera Corporation 18 _ 8.On page 1

43、0(Mem Init),click Yes,use this file for the memory content data.Once enabled,type in the file name ram.hex.This is the file you created in the previous step.Click Next._ 9.On page 11,the altera_mf simulation model file is displayed as being needed to simulate this function in a 3rd-party EDA simulat

44、ion tool.Click Next._ 10.Choose the same files to generate for ram as you did for mult earlier(Step 1,#11).Click Finish to close the wizard and then Yes to add the QIP file to the project.You have now created the two components needed for this design.Now you will create the HEX file needed to initia

45、lize the contents of the RAM.Quartus II Software Design Series:Foundation Exercises Copyright 2012 Altera Corporation 19 Step 4:Instantiate and connect design blocks according to design entry method Choose ONE of the following procedures based on your design entry method(VHDL,Verilog,or Schematic).F

46、ollow only the directions for your selected design entry method and then proceed to Step 5.VHDL _ 1.Open pipemult.vhd.You can use the Open command from the File menu,click the toolbar button,or double-click the top-level entity in the Project Navigator.You can also double-click Open Existing Design

47、File in the Create Design folder of the Tasks window.This is the top-level file for the design.Normally,you would have to instantiate both ram and mult and connect them together.In the interest of time,the file has been almost completed for you,but it is missing the instantiation of the multiplier._

48、 2.Open the file mult.cmp.Copy the component declaration from mult.cmp and paste it into the architecture declaration section of pipemult.vhd where indicated._ 3.Close mult.cmp._ 4.Open the file mult_inst.vhd.Copy the contents of mult_inst.vhd(the component instantiation)and paste into the architect

49、ure body of pipemult.vhd where indicated.Change the following signal names in the instantiation:clock_sig to clk1 dataa_sig to dataa datab_sig to datab result_sig to mult_to_ram _ 5.Close mult_inst.vhd._ 6.Save pipemult.vhd._ 7.Continue to Step 5:Check the design.Verilog _ 1.Open pipemult.v.You can

50、use the Open command from the File menu,click the toolbar button,or double-click the entity in the Project Navigator.You can also double-click Open Existing Design File in the Create Design folder of the Tasks window.This is the top-level file for the design.Normally,you would have to instantiate bo