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1、SC7731G PCB Design Guide V1.0.1Spreadtrum ConfidentialContent.2PMU Design GuideRF Design GuideSystem DiagramBaseBand Design GuideSpreadtrum Confidential.32014-9-15VersionDataAuthorDescriptionV1.0.02014.7.8sandyFirst versionV1.0.12014.9.3sandyChange the PMU VBAT layout requirementSpreadtrum Confident
2、ial.42014-9-15Table of ContentsPackagePackage sizeFootprint Signals distributionCommon design rules Stack upCommon rules Vias typeFan outPlacementHigh speed design rulesPDNDDREMMCRFPMUothersSpreadtrum ConfidentialPackage Size Information (SC7731G).52014-9-15Package info:1.Package size:13.3X12.1X0.9m
3、m max2.Ball pitch:0.4mm3.Ball diameter:0.25mm4.Ball count:597Spreadtrum ConfidentialFoot print.62014-9-15Footprint info:1.Ball diameter:0.25mm2.Ball pitch:0.4mm3.Solder mask opening:0.32mm4.Paster mast opening:0.27mmSpreadtrum ConfidentialSignals distribution.72014-9-15DDRNAND KEY,IIS,Trace,UARTCSI
4、EMMCDCDCDSISIM&SDUSBRF CTRLRF IQLDOAudioLDOSpreadtrum Confidential.82014-9-15Table of ContentsPackagePackage sizeFootprint Signals distributionCommon design rules Stack upCommon rules Vias typeFan outPlacementHigh speed design rulesPDNDDREMMCRFPMUothersSpreadtrum Confidential.92014-9-15PCB Layer sta
5、ckPCBIf need to adjust the thickness,please keep the thickness of PP,just adjust the thickness of CORE.Spreadtrum Confidential.102014-9-15PCB Layer stackPCBIf need to adjust the thickness,please keep the thickness of PP,just adjust the thickness of CORE.Spreadtrum ConfidentialCommon Design Rule.1120
6、14-9-15Internal chipAll layersExternal chipUnit:mmSpreadtrum ConfidentialVIA type.122014-9-15Laser via:Drill 0.1mmDiameter 0.25mmBuried via:Drill 0.25mmDiameter 0.45mmSpreadtrum ConfidentialPCB Fanout.132014-9-15The trace of outside two row/column balls routing from top layerPass three tracesSpreadt
7、rum ConfidentialPCB Fanout.142014-9-15Most of the traces of row/column 3,4,5 balls routing in layer2Pass five tracesSpreadtrum Confidential.152014-9-15Reference PlacementSC7731GLCDT FlashRF AntennaSIMCOF BT+WIFI+FM+GPSLPDDR2USBCameraBATRFSpreadtrum Confidential.162014-9-15Table of ContentsPackagePac
8、kage sizeFootprint Signals distributionCommon design rules Stack upCommon rules Vias typeFan outPlacementHigh speed design rulesPDNDDREMMCRFPMUothersSpreadtrum ConfidentialPDN Theory IntroducePower Delivery Network provide power for proper operation of the processor.The frequency of the processor is
9、 up to 1GHz even more high,the core quantity is from single core to quad cores,so the PDN become more and more critical.Generally the PDN include VRM(Voltage Regulation Module),decoupling capacitors,power plane(or trace)and GND plane.172014-9-15The purpose of PDN design is minimize the impedance ove
10、r the all frequency range，The target impedance can be defined asVRipple：the maximum allowed voltage variation for processorImax：the maximum currentSpreadtrum ConfidentialCapacitor Frquency Characteristics.182014-9-15A non-ideal capacitor can be modeled by combinations of capacitance,inductance and r
11、estistance.The right figure is the equivalent circuit.A typical capacitor frequency Response The black curve is the impedance characteristics of the combinationMulti capacitors combination frequency responseFrequencyMHzSpreadtrum ConfidentialPDN Impedance DistributionPCB design,decoupling capacitors
12、,chip package and chip design will dominate the PDN impedance in different frequency range:DC-300KHz:the PDN impedance is dominated by pcb and VRM300K-10MHz:the PDN impedance is dominated by pcb and decoupling capacitors10M-100MHz:the PDN impedance is dominated by decoupling capacitors and chip pack
13、age100M-1GHz:the PDN impedance is dominated by chip package and chip design1G:the PDN impedance is dominated by chip desig only.192014-9-15Note:the impedance distribution is theory value only Spreadtrum ConfidentialPDN Critical Path.202014-9-15The following figure is the PND model considering the pa
14、rasitic parameter.The Cbuck is the DCDC bypass capacitor,Cde is the decoupling capacitors.The dashed box is the PDN critical path,the loop effective inductance dominate the high fequency impedance.So the decoupling capacitors must be located as close to processor power pins as possible.It is strong
15、recommended that the decoupling capacitors are placed to the back-side of the power pins.The loop effective inductance is proportion to the loop area.BetterBestBadSpreadtrum ConfidentialStackupThe adjacent layer to power plane or trace must be whole GND plane,that can reduce the effective inducdance
16、,the recommended stack-up is:.212014-9-15Note:if need to modify the thickness,prefer to keep the distance betwen the powerplane and GND plane,the core thickness can be adjusted.Spreadtrum ConfidentialDCDC Design.222014-9-15LX trace must be short as far as possibleThe inductor and capacitor must be p
17、laced as close as possible DCDCs GND pins must use more than 12 blind vias and 6 buried vias to main GND planeSpreadtrum ConfidentialPCB Trace Width Design.232014-9-15Calculate the DC resistance of the trace can using the formula:：the copper electical resistivityL：trace lengthW：trace widthH：trace co
18、pper thicknessA common rule is 1mm width trace corresponding to 1A current.The VDDARM trace width must not less than 2mm,VDDCORE trace width must not less 1.5mm.These traces can be routed in different layer.HWLR=Spreadtrum ConfidentialVias Consideration.242014-9-15Calculate the minimum number of via
19、s require to carry the current.Typical blind via(0.1/0.25mm)and buried via(0.25/0.45mm)can be calculated according to 200mA/via and 400mA/via,the vddcore maximum current is about 2A,the vddarm maximum current is about 2A.The blind and buried vias should be uniform distribution,the proportion may be
20、1:2Bad：vias too fewBad：vias too intensiveGoodIn order to reduce vias ESL,GND vias should be placed as close to power vias as possible,the number of GND vias should equal to power vias at leastSpreadtrum ConfidentialDecoupling Capacitors Placement.252014-9-15Decoupling capacitors must be place as clo
21、se to power pins as possibleIt is the optimal to place some decoupling capacitors to backside power pinsThe decoupling capacitors include at least a 22uF,a 2.2uF and mutiple 0.1uF capacitorsThe distance between the decoupling capacitors and power pins must less than 7mmBadCaps far away from the powe
22、r pinBetterCaps close to the power pinBestCaps on the backside of power pinSpreadtrum ConfidentialDecoupling capacitors layout.262014-9-15Each capacitor terminal must be connected to main GND plane using vias directly,dont share the vias.The power vias should close to GND vias to reduce the loop ind
23、uctance.SC7731G chip GND pins must connect to main GND plane with vias,the number of vias is not less 20 blind vias and 10 buried viasThe trace width between capacitors and power pins should follow the 1A/mm rule,the adjacent layer must be whole GND plane.Around the trace should add more ground vias
24、.GoodBadSpreadtrum Confidential.272014-9-15SC7731G LPDDR2 Ball ListSignal NameTypeNumberDescriptionGroupingEMDQ0:31I/O32Bi-directional data busDQEMDQM0:3O4Output Data MaskEMDQS0:3/EMDQSN0:3I/O8Data Strobe(Bi-directional,Differential)EMA0:9O10Command/Address outputCAEMCKE0:1/EMCSN0:1O4Clock Enalble/C
25、hip SelectEMCLKDP/EMCLKDMO2Output Clock(Differential)VDDMEMPower9Provide IO power For LPDDR2 InterfacePOWERVDDREFPower1Provide reference Power For LPDDR2SC7731G LPDDR2 can support high speed data rate，PCB layout will be critical to SI,soit is strong recommended to comply with spreadtrums high speed
26、signal layout rule.Spreadtrum Confidential.282014-9-15MCP Placement RecommendationThe MCP should be placed close to SC7731G as possible,the distance between them should less than 2mm.7731GMCPSpreadtrum Confidential.292014-9-15Common PCB Design Guidelines For LPDDR2LPDDR2 common layout rule:1,Stripli
27、ne is strongly recommended2，Bellow SC7731G the route can follow 3mil/3mil rule，out of SC7731G the route rule keep 4mil/4mil 3，Adjacent layer signals dont overlap,orthogonality or interleave is prefered 4，Keep the same and solid reference plane above and below signals,the GND plane is preferred.Short
28、 the thickness between the signal and reference plane is prefered.5,Short the length of the trace is preferedSpreadtrum Confidential.302014-9-15PCB Design Guidelines For DQ/DQSByte0DQ0:7、DQM0、DQS0、DQSN0Byte1DQ8:15、DQM1、DQS1、DQSN1Byte2DQ16:23、DQM2、DQS2、DQSN2Byte3DQ24:31、DQM3、DQS3、DQSN3Route requireme
29、nt:1，Length requirement:Keep the same length of each byte,the maximum length difference is no more than+/-3mm in one byte keep the length difference within +/-3mm to all DQ,DQS,DQM 2,DQS and DQSN:keep the length difference within+/0.5mm,keep the traces symmetrickeep the distance of space between dif
30、ferential pairs constant over the entire length of the tracesAssign the GND around the differential pairs3,Assign all DQ,DQS,DQM on layer2 whatever stack-up struction,keep the Layer1 GND plane integrity especially for 4 layer stack-up.DQ and DQS can be divided into four Bytes:Byte0Byte1Byte2Byte3Spr
31、eadtrum Confidential.312014-9-15PCB Design Guidelines For CA1，Keep the same length of the CA traces,the length variation must be keeped within+/-3mm2，EMCLKDP/EMCLKDM:comply with the differential route rule,the length difference is no more than+/-0.5mmkeep the GND traces or plane around them3，Assign
32、the CA signals on Layer3 or Layer4 to all stack-up struction.Spreadtrum Confidential.322014-9-15Length controlDQ,DM to DQS(in a byte)3mmDQS to DQS(byte to byte)3mmDQS to DQS_N 0.5mmCLKDM to CLKDP0.5mmDQS to CLK 10mmAddress,control to CLK 3mmSpreadtrum ConfidentialPCB Design Guidelines For Power Plan
33、e1,Power plane for VDDMEM is mandatory，the plane must cover all LPDDR2 signals and SC7731Gs L9、M9、P9、R9、N9、T9、U9、V9、W9 pins2，Power vias and GND vias must be rectangular distribution,the proportion is at least 1:1,the GND vias must close to power vias in order to reduce loop inductance。3,At least use
34、 8 blind vias and 4 buried vias to connect power plane to SC7731Gs L9、M9、P9、R9、N9、T9、U9、V9、W9 pins.332014-9-15Power viasGND viasSpreadtrum ConfidentialPCB Design Guidelines For Power Plane.342014-9-15Keep a whole GND plane below or above the power plane,the distance between this two planes should be
35、 as short as possible.The recommended stack-up as follows:LayerThickness(um)Scenario IScenario IIL1Cu30SignalSignalDielectric72L2Cu30SignalSignalDielectric78L3Cu17GNDGNDCore200L4Cu17SignalSignalDielectric72L5Cu17GNDGNDCore200L6Cu17PowerSignalDielectric78L7Cu30SignalPowerDielectric72L8Cu30GNDGNDNot G
36、oodGoodLayerThickness(um)Scenario IScenario IIL1Cu30SignalSignalDielectric72L2Cu30SignalSignalDielectric121L3Cu17GNDGNDCore390L4Cu17PowerSignalDielectric121L5Cu30SignalPowerDielectric72L6Cu30GNDGNDNot GoodGoodSpreadtrum ConfidentialPCB Design Guidelines For LPDDR2 PDN.352014-9-151，Green trace width
37、must be no less than 1mm2,Cdeis key decoupling capacitors,the capacitors combination at least is a 10uF,a 2.2uF,four 0.1uF:1）dual-side placement：Strong recommend to place two 0.1uF capacitors back-side SC7731G power pins,two 0.1uF capacitors between SC7731G and LPDDR2.2）singe-side placement：at least
38、 place two 0.1uF capacitors between SC7731G and LPDDR2,the other capacitors loacate around the power plane Spreadtrum ConfidentialPCB Design Guidelines For LPDDR2 PDN.362014-9-15Each capacitor terminal must be connected to power plane and GND plane by vias directly,Dont share vias,the GND vias shoul
39、d close to power vias as possibleGoodBadSpreadtrum ConfidentialPCB Design Guidelines For EMMCSC7731G EMMC operation mode is 50MHz DDR，the pcb design requirments as follows:1，EMMC_CLK must be shielding by GND,far away the emmc_data0:72,Below or above the emmc bus must be a whole reference plane3,EMCC
40、 VDDI bypass capacitors must close to VDDI pin as possilbe.372014-9-15Spreadtrum Confidential.382014-9-15Table of ContentsPackagePackage sizeFootprint Signals distributionCommon design rules Stack upCommon rules Vias typeFan outPlacementHigh speed design rulesPDNDDREMMCRFPMUothersSpreadtrum Confiden
41、tialRF Design Guide 1/12.392014-9-151.RF SAW,DPX and PA close to SR31312.RF TX and RX trace need impedancecontrolDifferential 200 ohm Impedance50 ohm Impedance50 ohm ImpedanceRX is differential trace Spreadtrum ConfidentialRF Design Guide 2/12.402014-9-15Add more GND VIA For 4 layer PCB,L2 under RX
42、before SAW should be ground;for 6 layer PCB,L2 under the RX before SAW should be keep ground out，L3 should be ground.Spreadtrum Confidential3G Duplexer trace 3/12.412014-9-15q Add ground holes under 3G duplexer as more as possible,and keep the integrity of ground.q RX traces should avoid interfered
43、by TX and Ant trace.The Recommended traces is like the picture.Spreadtrum Confidential3G Duplexer trace 4/12-example.422014-9-15Left pic there is some ground trace/via issue compared with right pic,ground vias should be sufficient and Tx/Rx/Ant line should be shielding by ground trace.BadGoodSpreadt
44、rum Confidential3G Duplexer trace 5/12-example.432014-9-15Left pic there is component placement issue,matching components should be placed closely to duplexer,otherwise is will affect RF performance,the placement of right pic is more better.BadGoodSpreadtrum ConfidentialRF Design Guide 6/12.442014-9
45、-15PWR_DET1,PWR_DET2,PWR_DET5,PWR_DET8 should be protected by ground.It is better to be 50 ohm impedence control.Spreadtrum Confidential.452014-9-15RF Design Guide 7/12 IQ,RAMP traces should be protected by ground all around.Spreadtrum ConfidentialRF Design Guide 8/12.462014-9-15REF1_OUT,REF2_OUT an
46、d REF3_OUT are 26M CLK,the traces should be protected by ground.Spreadtrum ConfidentialRF Design Guide 9/12.472014-9-15SPI has 26M clk,the trace should be protected by ground.Spreadtrum ConfidentialRF Design Guide 10/12.482014-9-15Capacitors close to PA Power(VBAT)input PinCapacitors close to PA Pow
47、er(VWPA)input PinSpreadtrum ConfidentialRF Design Guide 11/12.492014-9-15VBAT for TD PA width 2mm.More than 4 buried vias,8 laser viasVWPA trace width 0.8mm,More than 2 buried vias,4 laser vias.Place enough GND VIA under PA,transcerverWVBAT trace width 0.3mmSpreadtrum Confidential26M Crystal 12/12.5
48、02014-9-15Keep out of copper pour under crystal signal pad and traces on L2 Spreadtrum Confidential.512014-9-15Table of ContentsPackagePackage sizeFootprint Signals distributionCommon design rules Stack upCommon rules Vias typeFan outPlacementHigh speed design rulesPDNDDREMMCRFPMUothersSpreadtrum Co
49、nfidentialRTC.522014-9-15Crystal placement close to SC7731,L2 should be Ground.L1 should shielding with ground.Spreadtrum Confidential.532014-9-15Power LDO bypass capacitors should place close to pin-out of baseband The GND pin of bypass capacitors should have vias to ground planeSpreadtrum Confiden
50、tial.54Power-VBAT The power should route in star-lines VBAT traces of BB should through ESD devices to the Battery connector A current should route mm.1 through via:500mASpreadtrum Confidential.552014-9-15Power-VBAT bypass capacitors should place close to BaseBand The GND pin of bypass capacitors sh