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1、-基于Xilinx_ISE的多功能数字钟实验报告-第 21 页多功能数字钟实验报告目录多功能数字钟实验报告1一、实验任务及要求31基本功能32拓展功能3二、实验条件31软件32开发板3三、电路的设计过程31工作原理与组成框图32单元电路设计3模块（1）计时与调时电路3模块（2）12-24小时转换电路：3模块（3）显示电路：3模块（4）报时电路：3模块（5）闹钟电路：33总体仿真波形3四、调试过程31.调试步骤32.调试中遇到的问题及解决办法33.最后观察到的实验结果3五、实验的收获、体会与改进建议3一、 实验任务及要求用FPGA器件和EDA技术实现多功能数字钟的设计1基本功能 以数字形式显示时
2、、分、秒的时间； 小时计数器为同步24进制； 要求手动校时、校分和自动校时、校分。2拓展功能 任意时刻闹钟； 小时显示（12/24）切换电路 仿广播电台正点报时； 自动报整点时数； 万年历； 秒表。二、 实验条件1软件：ISE13.42开发板：Basys2三、 电路的设计过程1 组成框图2 单元电路设计顶层模块：顶层模块是对所有模块的调用，源代码及注释如下：module top_clock(nCR,CP,show,sw,sel0,S1,S0,AH,AM,ledout,sp,led,sel0,sel1,sel2,clear,stop );/nCR为复位开关，CP500MHZ脉冲，show 7喂数
3、码管输出，sw四个数码管点亮选择，S1、S0调整按键，AH、AM调整拨码开关，ledout整点显示led，sp仿电台报时led，led闹钟显示led，sel0、sel1、sel2组合选择开关，clear秒清零开关，stop秒表停开关 input nCR,CP,S1,S0,AH,AM,sel0,sel1,sel2,clear,stop; output 6:0show; output 3:0sw; output 3:0ledout; output sp,led; wire 23:0cnt; wire 15:0cnt_out,stopsec; wire 15:0cnt_time; wire 15:0
4、cnt_alarm; wire 15:0year; wire 7:0month,day; second stoop(CP,stopsec,nCR,stop,clear);/秒表 date dt(cnt,CP,nCR,year,month,day,sel0,sel1,sel2,AM,AH);/万年历 TO_12 ampm(cnt23:8,cnt_time);/12-24进制转换 clock lclock(CP,cnt,S1,S0,nCR,AH,AM,sel0,sel1,sel2,clear);/报时即校时 show out_led(show,CP,sw,cnt_out);/译码 baoshi z
5、hengdian(CP,cnt,ledout,sp);/整点报时 alarm alarmset(cnt_alarm,S0,S1,AH,AM,nCR,CP,sel0,sel1,sel2);/闹钟 TAswitch AT(cnt_time,cnt_alarm,cnt,cnt_out,sel0,sel1,sel2,year,month,day,stopsec);/功能选择 time_alarm alled(cnt23:8,cnt_alarm,led,CP,nCR);/闹钟时间对比endmodule顶层模块图如下模块（1）计时与调时电路：计时模块中包含了计时调时模块和分频器模块，其中分频器模块的功能是
6、将50MHz的信号转化为1Hz的信号，实现秒脉冲功能；计时调时模块的功能包括将秒脉冲信号通过六进制计数器和十进制计数器转化为24位二进制的时分秒的形式（每四位一个数，一共六个数），同时通过手动调时和自动调时模块对信号进行调节。 源代码如下：/计时与调时模块module clock(CP,cnt,S1,S0,nCR,AH,AM,sel0,sel1,sel2,clear input S1,S0,CP,nCR,AH,AM,sel0,sel1,sel2,clear; output 23:0cnt; reg 3:0HH,HL,MH,ML,SH,SL; wire clk; secclk sec(CP,cl
7、k,nCR); assign cnt=HH,HL,MH,ML,SH,SL; always (posedge clk or negedge nCR) begin /自动调时部分 if(!nCR) begin HH=4b0000;HL=4b0000;MH=4b0000;ML=4b0000;SH=4b0000;SL=4b0000; end else begin if(AH&(!sel0)&(!sel1)&(!sel2) begin if(HH=4d2&HL=4d3) begin HH=4b0000; HL=4b0000; end else if(HL=4d9) begin HH=HH+4b0001;
8、 HL=4b0000; end else HL=HL+4b0001; end else if(AM&(!sel0)&(!sel1)&(!sel2) begin if(MH=4d5&ML=4d9) begin MH=4b0000; ML=4b0000; end else if(ML=4d9) begin MH=MH+4b0001; ML=4b0000; end else ML=ML+4b0001; end /秒清零部分else if(clear&(!sel0)&(!sel1)&sel2) begin SH=4b0000; SL=4b0000;end else begin /手动调时部分 if(S
9、1&(!sel0)&(!sel1)&(!sel2) begin if(HH=4d2&HL=4d3) begin HH=4b0000; HL=4b0000; end else if(HL=4d9) begin HH=HH+4b0001; HL=4b0000; end else HL=HL+4b0001; end /时钟部分 else if(S0&(!sel0)&(!sel1)&(!sel2) begin if(MH=4d5&ML=4d9) begin MH=4b0000; ML=4b0000; end else if(ML=4d9) begin MH=MH+4b0001; ML=4b0000;
10、end else ML=ML+4b0001; end else begin if(SL=4d9&SH=4d5) begin SL=4h0; SH=4h0; if(ML=4d9&MH=4d5) begin ML=4h0; MH=4h0; if(HH=4d2&HL=4d3) begin HH=4h0; HL=4h0; end else if(HL=4d9) begin HH=HH+4b0001; HL=4h0; end else HL=HL+4b0001; end else if(ML=4d9) begin ML=4h0; MH=MH+4b0001; end else ML=ML+4b0001;
11、end else if(SL=4d9) begin SH=SH+4b0001; SL=4b0000; end else SL=SL+4b0001; end end end endendmodule/秒脉冲分频器模块module secclk(clk_in,clk_out,nCR ); /clk_in和clk_out分别为信号的输入输出端，nCR为清零端 input clk_in,nCR ; output clk_out; reg 24:0cnt=25d0; reg clk_out=1b0; always (posedge clk_in or negedge nCR) begin if(nCR)
12、 cnt=25d0; else begin if(cnt=25d24999999) begin clk_out=clk_out;cnt=1d0; endelse cnt=cnt+1d1;end endendmodule波形图cnt为输出端，CP为原脉冲信号，S1为手动校时，S0为手动校分，nCR为清零，AH和AM为自动校时和校分。令S1=1，可见时钟在秒脉冲的上升沿从00:00:00变为01:00:00。模块（2）12-24小时转换电路： 12-24小时转换电路的原理是将12小时和24小时的显示模式进行相互转化，得到想要的显示。源代码如下：/12-24小时转换电路module TO_12(cn
13、t,cnt_out,switch );/cnt为输入信号，cnt_out为输出信号，switch为选择开关 input23:0cnt; input switch; output 23:0cnt_out; reg 23:0cnt_out; always(*) begin if(!switch) cnt_out=cnt; else begin case(cnt23:16)8b00000000:cnt_out23:16=8b0001_0010;8b00010011:cnt_out23:16=8b0000_0001;8b00010100:cnt_out23:16=8b0000_0010;8b00010
14、101:cnt_out23:16=8b0000_0011;8b00010110:cnt_out23:16=8b0000_0100;8b00010111:cnt_out23:16=8b0000_0101;8b00011000:cnt_out23:16=8b0000_0110;8b00011001:cnt_out23:16=8b0000_0111;8b00100000:cnt_out23:16=8b0000_1000;8b00100001:cnt_out23:16=8b0000_1001;8b00100010:cnt_out23:16=8b0001_0000;8b00100011:cnt_out2
15、3:16=8b0001_0001;default:cnt_out23:16=cnt23:16;endcasecnt_out15:0=cnt15:0; end end endmodule波形图如下：波形的第一行是输出的显示信号，第二行是输入信号（分别输入13:00:00和14:00:00，第三行是切换信号。可见在13:00时第一行输出的波形分别是13:00和1:00。模块（3）显示电路： 显示电路的原理是通过高速的扫描（1000Hz）让四个数码管轮流显示数字，从而让人眼产生错觉，认为数码管一直亮着。显示电路中包括显示模块、扫描模块和译码模块。扫描模块用来产生1000Hz的信号，相当于分频器。译码
16、模块可以将时钟信号转化成数码七段管的显示信号。显示模块通过不断的扫描将数字显示出来。源代码如下：/显示译码模块module show(show,CP ,sw,cnt_now input CP; input 15:0 cnt_now; output 6:0show; output 3:0sw; reg 1:0 Q=2b00; reg 3:0 num,sw; smCP smcp(CP,sm); always(posedge sm) begin case(Q) 2b00:begin num=cnt_now3:0; sw0=0; sw1=1; sw2=1; sw3=1; end 2b01: begin
17、 num=cnt_now7:4; sw0=1; sw1=0; sw2=1; sw3=1; end 2b10: begin num=cnt_now11:8; sw0=1; sw1=1; sw2=0; sw3=1; end 2b11:begin num=cnt_now15:12; sw0=1; sw1=1; sw2=1; sw3=0; endendcaseQ=Q+2b01;endtranslator trans(num,show);endmodule/扫描信号分频器模块（生成1000Hz的扫描信号）module smCP(clk_in,clk_out input clk_in; output cl
18、k_out; reg 24:0cnt=25d0; reg clk_out=1b0; always (posedge clk_in ) begin if(cnt=25d24999) begin clk_out=clk_out;cnt=1d0; endelse cnt=cnt+1d1; endendmodule/数码管译码器模块module translator(num,led);/num为输入信号，led为数码管的显示信号 input 3:0num; output 6:0led; reg 6:0led; always (*) case(num) 4b0000:led=7b0000001;4b00
19、01:led=7b1001111;4b0010:led=7b0010010;4b0011:led=7b0000110;4b0100:led=7b1001100;4b0101:led=7b0100100;4b0110:led=7b0100000;4b0111:led=7b0001111;4b1000:led=7b0000000;4b1001:led=7b0000100;default:led=7b0000000;endcaseendmodule波形图如下Show为输入数码管的波形，sw为数码管扫描开关，sel为切换时分或分秒，cnt为时间。模块（4）报时电路： 报时模块分为仿广播电台报时和整点报
20、时。仿广播电台的报时功能是在56秒亮，57秒熄灭，58秒亮，59秒熄灭，00秒亮三秒。整点报时的功能是在整点用二进制led显示当前时刻（如十点则亮1010）。整点报时功能基于十二小时制。 源代码如下：/报时模块module baoshi(CP,incnt,led_out,spark );/CP为扫描信号，incnt为当前时间，led_out为整点报时功能，spark为仿广播电台报时功能input CP;input 23:0incnt;output 3:0led_out;output spark;reg 3:0led_out;reg spark;/仿广播电台报时功能always (posedge
21、 CP) begin if(incnt15:0=16b0101100101010110)spark=1; else if(incnt15:0=16b0101100101010111)spark=0; else if(incnt15:0=16b0101100101011000)spark=1;else if(incnt15:0=16b0101100101011001)spark=0; else if(incnt15:0=16b0000000000000000)spark=1; else if(incnt15:0=16b0000000000000001)spark=1; else if(incnt
22、15:0=16b0000000000000010)spark=1; else spark=0; end/整点报时功能always (posedge CP) begin if (incnt23:0=24b000000010000000000000000)led_out=4b0001; else if (incnt23:0=24b000000100000000000000000)led_out=4b0010; else if (incnt23:0=24b000000110000000000000000)led_out=4b0011; else if (incnt23:0=24b0000010000
23、00000000000000)led_out=4b0100; else if (incnt23:0=24b000001010000000000000000)led_out=4b0101; else if (incnt23:0=24b000001100000000000000000)led_out=4b0110; else if (incnt23:0=24b000001110000000000000000)led_out=4b0111; else if (incnt23:0=24b000010000000000000000000)led_out=4b1000; else if (incnt23:
24、0=24b000010010000000000000000)led_out=4b1001; else if (incnt23:0=24b000100000000000000000000)led_out=4b1010; else if (incnt23:0=24b000100010000000000000000)led_out=4b1011; else if (incnt23:0=24b000100100000000000000000)led_out=4b1100; else if (incnt23:0=24b000100110000000000000000)led_out=4b0001; el
25、se if (incnt23:0=24b000101000000000000000000)led_out=4b0010; else if (incnt23:0=24b000101010000000000000000)led_out=4b0011; else if (incnt23:0=24b000101100000000000000000)led_out=4b0100; else if (incnt23:0=24b000101110000000000000000)led_out=4b0101; else if (incnt23:0=24b000110000000000000000000)led
26、_out=4b0110; else if (incnt23:0=24b000110010000000000000000)led_out=4b0111; else if (incnt23:0=24b001000000000000000000000)led_out=4b1000; else if (incnt23:0=24b001000010000000000000000)led_out=4b1001; else if (incnt23:0=24b001000100000000000000000)led_out=4b1010; else if (incnt23:0=24b0010001100000
27、00000000000)led_out=4b1011; else if (incnt23:0=24b001001000000000000000000)led_out=4b1100; else led_out=4b0000;endendmodule波形图如下：第一行为整点报时信号led_out，第二行为仿广播电台报时spark，第三行为脉冲，第四行为从01:59:56到02:00:02的时钟信号。波形检测了在01:59:56到02:00:02的报时状况，即整点报时0010，仿广播电台报时闪烁三次。模块（5）闹钟电路：闹钟电路由闹钟设置模块、闹钟时钟切换模块和闹钟报时模块三个大模块组成，其中闹钟设
28、置模块和闹钟报时模块又分别各包含一个秒脉冲模块。闹钟设置模块类似于计时模块中的设置部分，闹钟时钟切换模块用于切换显示。闹钟报时模块的功能是到达特定时刻点时led灯亮一分钟。源代码如下：/闹钟设置模块module alarm(cnt,S0,S1,AH,AM,nAR,CP,sel0,sel1,sel2 input S0,S1,nAR,AH,AM,CP,sel0,sel1,sel2; output 15:0cnt; reg 3:0HH,HL,MH,ML; wire clk; secclk second(CP,clk,nAR); assign cnt=HH,HL,MH,ML; always (pose
29、dge clk) begin if(!nAR) begin HH=4b0000;HL=4b0000;MH=4b0000;ML=4b0000; end else begin if(AH&sel0&(!sel1)&(!sel2) begin if(HH=4d2&HL=4d3) begin HH=4b0000; HL=4b0000; end else if(HL=4d9) begin HH=HH+4b0001; HL=4b0000; end else HL=HL+4b0001; end else if(AM&sel0&(!sel1)&(!sel2) begin if(MH=4d5&ML=4d9) b
30、egin MH=4b0000; ML=4b0000; end else if(ML=4d9) begin MH=MH+4b0001; ML=4b0000; end else ML=ML+4b0001; endelse begin if(S1&sel0&(!sel1)&(!sel2) begin if(HH=4d2&HL=4d3) begin HH=4b0000; HL=4b0000; end else if(HL=4d9) begin HH=HH+4b0001; HL=4b0000; end else HL=HL+4b0001; end else if(S0&sel0&(!sel1)&(!se
31、l2) begin if(MH=4d5&ML=4d9) begin MH=4b0000; ML=4b0000; end else if(ML=4d9) begin MH=MH+4b0001; ML=4b0000; end else ML=ML+4b0001; endend end endendmodule/闹钟报时模块module time_alarm(cnt0,cnt1,led,CP,nCR input 23:0cnt0,cnt1; input CP,nCR; output led; reg led; reg 2:0count=3d0; secclk second(CP,clk,nCR);
32、always (posedge clk) begin if(!nCR) begin led=0; count=3d0; end else if(cnt0=cnt1) begin led=1;count3d0)&(count3d5) begin led=1;count=count+3d1; end else begin led=0;count=3d0; end endendmodule波形图如下（仅检测闹钟的报时模块）：即当cnt0与cnt1相同时输出led为1模块（6）万年历module date(clock,CP,nCR,year,month,day,sel0,sel1,sel2,AD,AM
33、 input nCR,CP,AD,AM,sel0,sel1,sel2; input23:0 clock; output15:0year; output8:0month,day; reg15:0year; reg8:0month,day; reg a,d; secclk sec(CP,clk,nCR); always (*) begin if(year&16b0000000011111111) begin if(4d10*year7:4+year3:0)%4=0) a=1;else a=0;endelse begin if(4d10*year15:12+year11:8)%4=0) a=1;el
34、se a=0;end end always (posedge clk or negedge nCR) begin if(!nCR) begin year=16b0010_0000_0001_0011;month=8b0000_0001; day=8b0000_0001; end else begin if(AD&sel0&sel1&(!sel2) begin if(year3:0=4b1001) begin year3:0=4b0000; if(year7:4=4b1001) begin year7:4=4b0000; if(year11:8=4b1001) begin year11:8=4b
35、0000; if(year15:12=4b1001) year15:12=4b0000; else year15:12=year15:12+4b0001;endelse year11:8=year11:8+4b0001; end else year7:4=year7:4+4b0001; end else year3:0=year3:0+4b0001; endif(AM&sel0&sel1&(!sel2) begin if(year3:0=4b0000) begin year3:0=4b1001; if(year7:4=4b0000) begin year7:4=4b1001; if(year1
36、1:8=4b0000) begin year11:8=4b1001; if(year15:12=4b0000) year15:12=4b1001; else year15:12=year15:12-4b0001;endelse year11:8=year11:8-4b0001; end else year7:4=year7:4-4b0001; end else year3:0=year3:0-4b0001; end if(AD&sel0&sel1&sel2) d=1;else d=0;if(AM&sel0&sel1&sel2) begin if(month=8b00010010) month=
37、8b00000001; else if(month=8b00001001) month=8b00010000; else month3:0=month3:0+4b0001;end if(clock=24b0010_0011_0101_1001_0101_1001|d) begin if(month=8b0000_0001)|(month=8b0000_0011)|(month=8b0000_0101)|(month=8b0000_0111)|(month=8b0000_1000)|(month=8b0001_0000)|(month=8b0001_0010)&(day=8b00110001) begin day=8b0000_0001; if(month=8b0001_0010) begin