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1、-基于FPGA的基于DDS技术的信号发生器设计-第 17 页 JIANGSU UNIVERSITY OF TECHNOLOGY FPGA技术实验报告基于FPGA的基于DDS技术的信号发生器设计 学 院： 电信学院 专 业： 电子信息工程 班 级： 11电子2班 姓 名： 学 号 : 指导教师： 朱雷、陈海忠 设计时间: _2014年2月16日2014年2月28日目录1 FPGA硬件系统设计1.1 功能要求1.2 FPGA硬件系统组成1.3 FPGA最小系统简介1.4 FPGA外围电路设计1.4.1 拨码开关电路设计1.5 硬件电路调试及结果分析2基于DDS技术的信号发生器设计2.1 功能要求2
2、.2 整体设计2.3 DDS技术的基本原理2.4 程序设计2.4.1 方波产生程序设计及仿真2.4.2 三角波产生程序设计及仿真2.4.3 正弦波产生程序设计及仿真2.4.4 锯齿波产生程序设计及仿真2.4.5 AM产生程序设计及仿真2.4.6 DSB产生程序设计及仿真2.4.7 DSB产生程序设计及仿真2.4.8 DSB产生程序设计及仿真2.4.9 DSB产生程序设计及仿真2.4.10 DSB产生程序设计及仿真2.4.7 顶层程序设计及仿真(1) 程序的功能(2) 结构图或实体图(3) VHDL程序及注释(4) 仿真波形及分析2.5 硬件测试及结果分析3设计分析与总结3.1 故障分析3.2功
3、能分析3.3 设计总结及感想1 FPGA硬件系统设计1.1 功能要求基于FPGA的DDS技术设计正弦波、三角波、方波等波形发生器 ，实现波形的D/A转换，实现改变高低电平开关电路设计。1.2 FPGA硬件系统组成FPG最小系统实现软件的写入，外围电路实现开关电路和D/A转换。1.3 FPGA最小系统简介通过APS接口下载程序到FPGA。1.4 FPGA外围电路设计1.4.1 拨码开关电路设计用开关控制输出高低电平。FPGA/CPLD芯片1.4.3 DAC0832电路设计DAC0832是采用CMOS/Si-Cr工艺实现的8位D/A转换器。该芯片包含8位输入寄存器、8位DAC寄存器、8位D/A转换
4、器。DAC0832中有两级锁存器，第一级即输入寄存器，第二级即DAC寄存器，可以工作在双缓冲方式下。 引脚特性：D7D0：8位数据输入端ILE：输入寄存器锁存允许信号CS#：芯片选择信号WR1#：输入寄存器写信号XFER#：数据传送信号WR2#：DAC寄存器写信号VREF：基准电压，-10V+10VRfb：反馈信号输入端IOUT1:电流输出1端IOUT2:电流输出2端VCC：电源AGND：模拟地DGND：数字地 1.5 硬件电路调试及结果分析硬件焊接时，容易将焊点漏焊或则连接在一起。第一次焊好是先发没有输出波形。经过检查发现是输出插针没有与输出端口焊好。经过重新焊接后就可以输出波形了。2基于D
5、DS技术的信号发生器设计2.1 功能要求基于FPGA的DDS技术设计正弦波、三角、方波、锯齿波发生器。 2.2 整体设计2.3 DDS技术的基本原理1)频率预置与调节电路作用：实现频率控制量的输入；不变量K被称为相位增量，也叫频率控制字。2)累加器相位累加器的组成= N位加法器+N位寄存器相位累加器的作用：在时钟的作用下，进行相位累加注意：当相位累加器累加满量时就会产生一次溢出，完成一个周期性的动作。DDS的输出频率为：f0=fCK/2NDDS输出的最低频率：K=1时，fC/2NDDS输出的最高频率：Nyquist采样定理决定，即fC/2， K的最大值为2N-1结论：只要N足够大，DDS可以得
6、到很细的频率间隔。要改变DDS的输出频率，只要改变频率控制字K即可。2.4 程序设计2.4.1 方波产生程序设计及仿真通过C+做一个方波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出fangbo.exe后缀的文件将其转换为fangbo.mif，通过quarter将后缀fangbo.mif文件做成ROM后，会得到fangbo.vhd。编译后仿真得到如下波形。程序LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY fangbo ISPORTaddress: IN
7、STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END fangbo;ARCHITECTURE SYN OF fangbo ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_fam
8、ily: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURALPORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNT
9、O 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = fangbo.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width
10、_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.2 三角波产生程序设计及仿真通过C+做一个三角波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出sanjiao.exe后缀的文件将其转换为三角.mif，通过quarter将后缀sanjiao.mif文件做成ROM后，会得到sanjiao.vhd。编译后仿真得到如下波形。程序LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE alter
11、a_mf.all;ENTITY sanjiaobo ISPORTaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END sanjiaobo;ARCHITECTURE SYN OF sanjiaobo ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_outp
12、ut_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURALPORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECT
13、OR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = sanjiaobo.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_r
14、eg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.3 正弦波产生程序设计及仿真通过C+做一个正弦波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出sin.exe后缀的文件将其转换为sin.mif，通过quarter将后缀sin.mif文件做成ROM后，会得到sin.vhd。编译后仿真得到如下波形。程序LIBRARY ieee;USE ieee.std_
15、logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY myrom1 ISPORTaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END myrom1;ARCHITECTURE SYN OF myrom1 ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_
16、input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_byteena_a: NATURALPORT (clock0: IN STD_LO
17、GIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = myrom1.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,o
18、utdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.4锯齿产生程序设计及仿真通过C+做一个锯齿波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出juchi.exe后缀的文件将其转换为juchi.mif，通过quarter将后缀juchi.mif文件做成ROM后，会得到juchi.vhd。编译后仿
19、真得到如下波形。程序LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY juchibo ISPORTaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END juchibo;ARCHITECTURE SYN OF juchibo ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 DOWNTO 0);COM
20、PONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATURAL;width_by
21、teena_a: NATURALPORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = juchibo.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = altsyncram,
22、numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.5 AM产生程序设计及仿真通过C+做一个方波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出AM.exe后缀的文件将其转换为AM.mif，通过quarter将后缀A
23、M.mif文件做成ROM后，会得到AMvhd。编译后仿真得到如下波形。程序LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY am ISPORTaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END am;ARCHITECTURE SYN OF am ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (9 D
24、OWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURAL;width_a: NATU
25、RAL;width_byteena_a: NATURALPORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = am.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO,lpm_type = alts
26、yncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.6 DSB产生程序设计及仿真通过C+做一个方波的ROM，输入是1024个（）,输出为10位（），编译运行后，找出DSB.exe后缀的文件将其转换为DSB.mif，通过q
27、uarter将后缀DSB.mif文件做成ROM后，会得到DSB.vhd。编译后仿真得到如下波形。程序IBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.all;ENTITY ssb ISPORTaddress: IN STD_LOGIC_VECTOR (9 DOWNTO 0);clock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END ssb;ARCHITECTURE SYN OF ssb ISSIGNAL sub_wire0: STD_LO
28、GIC_VECTOR (9 DOWNTO 0);COMPONENT altsyncramGENERIC (clock_enable_input_a: STRING;clock_enable_output_a: STRING;init_file: STRING;intended_device_family: STRING;lpm_hint: STRING;lpm_type: STRING;numwords_a: NATURAL;operation_mode: STRING;outdata_aclr_a: STRING;outdata_reg_a: STRING;widthad_a: NATURA
29、L;width_a: NATURAL;width_byteena_a: NATURALPORT (clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (9 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)END COMPONENT;BEGINq BYPASS,clock_enable_output_a = BYPASS,init_file = ssb.mif,intended_device_family = Cyclone II,lpm_hint = ENABLE_RUNTIME_MOD=NO
30、,lpm_type = altsyncram,numwords_a = 1024,operation_mode = ROM,outdata_aclr_a = NONE,outdata_reg_a = UNREGISTERED,widthad_a = 10,width_a = 10,width_byteena_a = 1PORT MAP (clock0 = clock,address_a = address,q_a = sub_wire0END SYN;2.4.7 选择波形程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGI
31、C_UNSIGNED.ALL;ENTITY chiose IS PORT(c1,c2,c3,c4,c5,c6:IN std_logic_vector(9 DOWNTO 0);-复位信号reset， 时钟信号clkcho:in std_logic_vector(2 DOWNTO 0);q:OUT std_logic_vector(9 DOWNTO 0);-输出信号qEND chiose;ARCHITECTURE b OF chiose ISbeginq= c1 when cho=0 elsec2 when cho=1 elsec3 when cho=2 elsec4 when cho=3 els
32、ec5 when cho=4 elsec6 when cho=5 else0000000000 ;end b;2.4.8 32位加法器程序设计LIBRARY IEEE; -32位加法器模块USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER32B IS PORT (A,B : IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );END ADDER32B;ARCHITECTURE behav OF ADDER3
33、2B IS BEGINS = A + B;END behav;2.4.9 10位加法器程序设计LIBRARY IEEE; -10位加法器模块USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ADDER10B IS PORT (A,B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );END ADDER10B;ARCHITECTURE behav OF ADDER10B IS BEGINS = A + B;END b
34、ehav; 2.4.10 32位寄存器器程序设计LIBRARY IEEE; -32位寄存器模块USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG32B IS PORT ( Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) );END REG32B;ARCHITECTURE behav OF REG32B ISBEGIN PROCESS(Load, DIN) BEGIN IF LoadEVENT AND Load =
35、1 THEN DOUT = DIN; END IF; END PROCESS;END behav; 2.4.11 10位寄存器器程序设计LIBRARY IEEE; -10位寄存器模块USE IEEE.STD_LOGIC_1164.ALL;ENTITY REG10B IS PORT ( Load : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );END REG10B;ARCHITECTURE behav OF REG10B ISBEGIN PROCESS
36、(Load, DIN) BEGIN IF LoadEVENT AND Load = 1 THEN DOUT = DIN; END IF; END PROCESS;END behav; 2.4.12 顶层程序设计及仿真 (1) 程序的功能通过顶层程序将每个子程序联系起来，从而实现分频，输出不同波形，调相等功能。(2) 结构图或实体图(3) VHDL程序及注释LIBRARY IEEE; -DDS顶层设计USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY DDS_VHDL IS PORT ( CLK : IN STD_
37、LOGIC; -时钟信号 sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -选择输出波形 FWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -频率控制字 PWORD : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -相位控制字 FOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); END;ARCHITECTURE one OF DDS_VHDL IS COMPONENT ADDER32B PORT ( A : IN STD_LOGIC_VECTOR(31 DOWNTO 0); B :
38、 IN STD_LOGIC_VECTOR(31 DOWNTO 0); S : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG32B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT; COMPONENT REG10B PORT ( LOAD : IN STD_LOGIC; DIN : IN STD_LOGIC_VECTOR(9 DOWNTO 0); DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) ); END COMPONENT; COMPONENT ADDER10B PORT ( A : IN STD_LOGIC_VECTOR(9 DOWNTO 0); B : IN STD_LOGIC_VECTOR(9 DOWNTO 0); S : OUT