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1、P1.1. To express each equation as sum-of-product and as a product-of-sum first write the truth table then create a Karnaugh map from the truth table. Then use the 1s for sum-of products and 0s for product of sums.ABCF00000010010001111000101111011111Table P 1CAB000111100001010111Table P 2Collecting t
2、he terms together we find:DAC000111100001111100Table P 3Collecting the terms together we find:P1.2. There are many ways to do the circuit, heres one version. First create a truth table.ABCF00000011010101101001101011001111Table P 3The Boolean equation is: .a. All NAND circuit (yours may be slightly d
3、ifferent) is shown below:b. All NOR circuit:P1.3. There are many ways to do the circuits, heres one version.See solution to P1.2 for guidance.a. Implementing the truth table into K-Map form:AB00011110Sum0101Carry0010Table P 4the resulting Boolean equations are:b. The associated gate equivalent will
4、be:Figure P 1P1.4. First, the full adder truth table:ABCINCOUTSum0000000101010010111010001101101101011111Table P 5a. Implementing the truth table into K-Map form:ABCIN000111100010111010Table P 6: Sum K-MapABCIN000111100001010111Table P 7: COUT K-Mapb. The associated gate equivalent is straight-forwa
5、rd based on the previous problems.P1.5. This question is as easy as it looks, no tricks here.a. The delay from a to b is simply the delay of an inverter times the number of inverters which would be 10 ns.i. The period in this case is simply twice the delay around the loop, T=20 ns. ii. The frequency
6、 is 1/T =50 MHz.P1.6. The delay of an RC circuit with a step input applied is:In our case, we are solving for t:a. For V(t)=0.6V:b. 1.2V:This circuit will never read 1.2V.c. The delay from 10% to 90% VDD:P1.7. The delay for a and b uses the exponential rise/fall equation:a. For RDOWN:b. For RUP:c. T
7、he ratio of delays is:or 0.42 (depending on which way you did the ratio.)P1.8. Since Moores Law states that the transistor density doubles with each technology node, the number of transistors that can be integrated at 0.13m is 100 million.P1.9. At the current technology node, the processor speed is
8、2GHz. The next technology nodes will see 4GHz, 8GHz, 16GHz and 32GHz. Therefore it will take 4 generations to reach this speed. Note that the speed is only increasing by a factor of 1.4 rather than 2.Since every technology node takes 3 years, it would take 12 years to reach 30 GHz.P1.10. The current equation for a current source charging and ideal capacitor is:Since the current of the source is constant, the equation for the current can be simplified to: