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1、-EDA数字时钟设计-第 5 页Quartus数字时钟设计一. 设计功能1. 可以快速设置时钟起始值；2. 在59分50秒时开始报时，七声低音，一声高音，报完刚好整点。1.顶层设计（采用BDF文件图形设计，文件名：timer.bdf）2. 秒计时器模块设计library ieee;use ieee.std_logic_1164.all;ith.all; use ieee.std_logic_unsigned.all;entity second1 isport(clk1s:in std_logic; reset:in std_logic; sec2,sec1:buffer std_logic_v
2、ector(3 downto 0);-秒的十位和个位 seco: out std_logic); -秒计时器的进位输出end;architecture A of second1 is begin process(clk1s,reset) begin if reset = 0 then sec2 = 0000; sec1 = 0000; -清零秒计时器 seco = 0; elsif clk1sevent and clk1s =1 then if (sec1 = 1001 and sec2 = 0101) then sec2 = 0000;sec1 =0000; -在59秒时回零 seco =
3、1; -进位 elsif (sec1 =1001) then sec1 =0000; sec2 = sec2+1; seco = 0; else sec1 = sec1+1; seco = 0; end if; end if;end process;end;library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;entity minute1 isport(clkm,clk1s,setm:in std_logic; -秒进位输入，1HZ校分时钟输
4、入信号，校分控制信号 min2,min1:buffer std_logic_vector(3 downto 0); -分计时器的十位和个位 minco:out std_logic);end;architecture A of minute1 is signal clkx:std_logic; begin Pclkm:process(clkm,clk1s,setm) begin -根据是否校分选择计时时钟 if setm =1 then clkx = clk1s; -利用clk1s信号对分的初值进行快速设置 else clkx =clkm; -利用秒的进位信号正常计时 end if;end pr
5、ocess;Pcontm:process(clkx) begin if clkxevent and clkx =1 then if (min1 = 1001 and min2 = 0101) then min1 =0000;min2 =0000;minco =1; -59分时回零并进位 elsif (min1 = 1001) then min1 =0000;min2 = min2+1; minco = 0; else min1 = min1+1;minco =0; end if; end if;end process;end;library ieee;use ieee.std_logic_11
6、64.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;entity hour1 is port(clkh,clk1s,seth:in std_logic; hou2,hou1:buffer std_logic_vector(3 downto 0) ); -时的十位和个位end;architecture A of hour1 is signal clky:std_logic; begin Pclkh:process(clkh,clk1s,seth) Begin -根据是否校时选择计时时钟 if seth =1
7、then clky =clk1s; -利用clk1s信号对时的初值进行快速设置 else clky = clkh; -利用分的进位信号正常计时 end if; end process;Pconth:process(clky) begin if clkyevent and clky =1 then if (hou1=0011 and hou2 =0010 ) then hou1 = 0000;hou2 = 0000; -23时回零 elsif (hou1 =1001) then hou1 = 0000; hou2 = hou2+1; else hou1 flag500:=1; when 0010
8、 = flag500:=1; when 0100 = flag500:=1; when 0110 = flag500:=1; when 0111 = flag500:=1; when 1000 = flag500:=1; when 1001 = flag500:=1; -50,52,54,56,58,59秒时低频率报时 when others = flag500:=0;flag1k:=0; end case; else flag500:=0;flag1k:=0; end if; if (min1 =0000 and min2=0000 and sec1=0000 and sec2=0000)
9、then flag1k:=1; -整点时高频率报时 end if; end if;if flag500=1 then alarm =clk500; elsif flag1k=1 then alarm =clk1k; else alarm =0;end if;end process;end;1. 秒计时器仿真结果2. 分计时器仿真结果3. 时计时器仿真结果4. 报时模块仿真结果1.仿真结果中，由于输出信号向量（比如sec1(0),sec1(1),sec1(2),sec1(3)）变化的不同时，使得组合后的sec1，sec2，min1，min2均出现毛刺，尝试了引入中间变量，中间信号的方法，都不能解决问题。怎么办才好？