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1、外文文献原文：Ask The Application Engineer33All About Direct Digital SynthesisBy Eva Murphy, (eva.murphy)Colm Slattery (colm.slattery)By Analog Dialogue Volume 38 Number 3 of ADIWhat is Direct Digital Synthesis?Direct digital synthesis (DDS) is a method of producing an analog waveformusually a sine waveby
2、generating a time-varying signal in digital form and then performing a digital-to-analog conversion. Because operations within a DDS device are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. Wi
3、th advances in design and process technology, todays DDS devices are very compact and draw little power.Why would one use a direct digital synthesizer (DDS)? Arent there other methods for easily generating frequencies?The ability to accurately produce and control waveforms of various frequencies and
4、 profiles has become a key requirement common to a number of industries. Whether providing agile sources of low-phase-noise variable-frequencies with good spurious performance for communications, or simply generating a frequency stimulus in industrial or biomedical test equipment applications, conve
5、nience, compactness, and low cost are important design considerations.Many possibilities for frequency generation are open to a designer, ranging from phase-locked-loop (PLL)-based techniques for very high-frequency synthesis, to dynamic programming of digital-to-analog converter (DAC) outputs to ge
6、nerate arbitrary waveforms at lower frequencies. But the DDS technique is rapidly gaining acceptance for solving frequency- (or waveform) generation requirements in both communications and industrial applications because single-chip IC devices can generate programmable analog output waveforms simply
7、 and with high resolution and accuracy.Furthermore, the continual improvements in both process technology and design have resulted in cost and power consumption levels that were previously unthinkably low. For example, the AD9833, a DDS-based programmable waveform generator (Figure 1), operating at
8、5.5 V with a 25-MHz clock, consumes a maximum power of 30 milliwatts.Figure 1. The AD9833a one-chip waveform generator.What are the main benefits of using a DDS?DDS devices like the AD9833 are programmed through a high speed serial peripheral-interface (SPI), and need only an external clock to gener
9、ate simple sine waves. DDS devices are now available that can generate frequencies from less than 1 Hz up to 400 MHz (based on a 1-GHz clock). The benefits of their low power, low cost, and single small package, combined with their inherent excellent performance and the ability to digitally program
10、(and reprogram) the output waveform, make DDS devices an extremely attractive solutionpreferable to less-flexible solutions comprising aggregations of discrete elements.What kind of outputs can I generate with a typical DDS device?DDS devices are not limited to purely sinusoidal outputs. Figure 2 sh
11、ows the square-, triangular-, and sinusoidal outputs available from an AD9833.Figure 2. Square-, triangular-, and sinusoidal outputs from a DDS.How does a DDS device create a sine wave?Heres a breakdown of the internal circuitry of a DDS device: its main components are a phase accumulator, a means o
12、f phase-to-amplitude conversion (often a sine look-up table), and a DAC. These blocks are represented in Figure 3.Figure 3. Components of a direct digital synthesizer.A DDS produces a sine wave at a given frequency. The frequency depends on two variables, the reference-clock frequency and the binary
13、 number programmed into the frequency register (tuning word).The binary number in the frequency register provides the main input to the phase accumulator. If a sine look-up table is used, the phase accumulator computes a phase (angle) address for the look-up table, which outputs the digital value of
14、 amplitudecorresponding to the sine of that phase angleto the DAC. The DAC, in turn, converts that number to a corresponding value of analog voltage or current. To generate a fixed-frequency sine wave, a constant value (the phase incrementwhich is determined by the binary number) is added to the pha
15、se accumulator with each clock cycle. If the phase increment is large, the phase accumulator will step quickly through the sine look-up table and thus generate a high frequency sine wave. If the phase increment is small, the phase accumulator will take many more steps, accordingly generating a slowe
16、r waveform.Lets talk some more about the phase accumulator. How does it work?Continuous-time sinusoidal signals have a repetitive angular phase range of 0 to 2. The digital implementation is no different. The counters carry function allows the phase accumulator to act as a phase wheel in the DDS imp
17、lementation.To understand this basic function, visualize the sine-wave oscillation as a vector rotating around a phase circle (see Figure 4). Each designated point on the phase wheel corresponds to the equivalent point on a cycle of a sine wave. As the vector rotates around the wheel, visualize that
18、 the sine of the angle generates a corresponding output sine wave. One revolution of the vector around the phase wheel, at a constant speed, results in one complete cycle of the output sine wave. The phase accumulator provides the equally spaced angular values accompanying the vectors linear rotatio
19、n around the phase wheel. The contents of the phase accumulator correspond to the points on the cycle of the output sine wave.Figure 4. Digital phase wheel.The phase accumulator is actually a modulo-M counter that increments its stored number each time it receives a clock pulse. The magnitude of the
20、 increment is determined by the binary-coded input word (M). This word forms the phase step size between reference-clock updates; it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and completes its equivalent of a
21、 sine-wave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28-bit phase accumulator, an M value of 0000.0001 would result in the phase accumulator overflowing
22、 after 228 reference-clock cycles (increments). If the M value is changed to 0111.1111, the phase accumulator will overflow after only 2 reference-clock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:where:fOUT = output frequenc
23、y of the DDSM = binary tuning wordfC = internal reference clock frequency (system clock)n = length of the phase accumulator, in bitsChanges to the value of M result in immediate and phase-continuous changes in the output frequency. No loop settling time is incurred as in the case of a phase-locked l
24、oop.As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the
25、 output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output.When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp.T
26、hen how is that linear output translated into a sine wave?A phase-to-amplitude lookup table is used to convert the phase-accumulators instantaneous output value (28 bits for AD9833)with unneeded less-significant bits eliminated by truncationinto the sine-wave amplitude information that is presented
27、to the (10-bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a complete sine wave from one-quarter-cycle of data from the phase accumulator. The phase-to- amplitude lookup table generates the remaining data by reading for
28、ward then back through the lookup table. This is shown pictorially in Figure 5.Figure 5. Signal flow through the DDS architecture.What are popular uses for DDS?Applications currently using DDS-based waveform generation fall into two principal categories: Designers of communications systems requiring
29、 agile (i.e., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its combination of spectral performance and frequency-tuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance over
30、all frequency tunability, as a local oscillator (LO), or even for direct RF transmission.Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted wi
31、thout the need to change the external components that would normally need to be changed when using traditional analog-programmed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or compensate for temperature drift. Such applications include
32、 using a DDS in adjustable frequency sources to measure impedance (for example in an impedance-based sensor), to generate pulse-wave modulated signals for micro-actuation, or to examine attenuation in LANs or telephone cables.What do you consider to be the key advantages of DDS to designers of real-
33、world equipment and systems?Todays cost-competitive, high-performance, functionally integrated DDS ICs are becoming common in both communication systems and sensor applications. The advantages that make them attractive to design engineers include: digitally controlled micro-hertz frequency-tuning an
34、d sub-degree phase-tuning capability, extremely fast hopping speed in tuning output frequency (or phase); phase-continuous frequency hops with no overshoot/undershoot or analog-related loop settling-time anomalies, the digital architecture of DDS eliminates the need for the manual tuning and tweakin
35、g related to component aging and temperature drift in analog synthesizer solutions, and the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control.How would I use a DDS device fo
36、r FSK encoding?Binary frequency-shift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is desi
37、gnated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the mark-space data and the transmitted signal.Figure 6. FSK modulation.This encoding scheme is easily implemented using a DDS. The DDS frequency t
38、uning word, representing the output frequencies, is set to the appropriate values to generate f0 and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the two required tuning words into the device before transmission. In the case of the AD9834, two frequency registers
39、 are available to facilitate convenient FSK encoding. A dedicated pin on the device (FSELECT) accepts the modulating signal and selects the appropriate tuning word (or frequency register). The block diagram in Figure 7 demonstrates a simple implementation of FSK encoding.Figure 7. A DDS-based FSK en
40、coder.And how about PSK coding?Phase-shift keying (PSK) is another simple form of data encoding. In PSK, the frequency of the carrier remains constant and the phase of the transmitted signal is varied to convey the information.Of the schemes to accomplish PSK, the simplest-known as binary PSK (BPSK)
41、uses just two signal phases: 0 degrees and 180 degrees. BPSK encodes 0 phase shift for a logic 1 input and 180 phase shift for a logic 0 input. The state of each bit is determined according to the state of the preceding bit. If the phase of the wave does not change, the signal state stays the same (
42、low or high). If the phase of the wave reverses (changes by 180 degrees), then the signal state changes (from low to high, or from high to low).PSK encoding is easily implemented with DDS ICs. Most of the devices have a separate input register (a phase register) that can be loaded with a phase value
43、. This value is directly added to the phase of the carrier without changing its frequency. Changing the contents of this register modulates the phase of the carrier, thus generating a PSK output signal. For applications that require high speed modulation, the AD9834 allows the preloaded phase regist
44、ers to be selected using a dedicated toggling input pin (PSELECT), which alternates between the registers and modulates the carrier as required.More sophisticated forms of PSK employ four- or eight- wave phases. This allows binary data to be transmitted at a faster rate per phase change than is poss
45、ible with BPSK modulation. In four-phase modulation (quadrature PSK or QPSK), the possible phase angles are 0, +90, 90, and 180 degrees; each phase shift can represent two signal elements. The AD9830, AD9831, AD9832, and AD9835 provide four phase registers to allow complex phase modulation schemes t
46、o be implemented by continuously updating different phase offsets to the registers.Can multiple DDS devices be synchronized for, say, I-Q capability?It is possible to use two single DDS devices that operate on the same master clock to output two signals whose phase relationship can then be directly
47、controlled. In Figure 8, two AD9834s are programmed using one reference clock, with the same reset pin being used to update both parts. Using this setup, it is possible to do I-Q modulation.Figure 8. Multiple DDS ICs in synchronous mode.A reset must be asserted after power-up and prior to transferri
48、ng any data to the DDS. This sets the DDS output to a known phase, which serves as the common reference point that allows synchronization of multiple DDS devices. When new data is sent simultaneously to multiple DDS units, a coherent phase relationship can be maintained, and their relative phase off
49、set can be predictably shifted by means of the phase-offset register. The AD9833 and AD9834 have 12 bits of phase resolution, with an effective resolution of 0.1 degree.What are the key performance specs of a DDS based system?Phase noise, jitter, and spurious-free dynamic range (SFDR).Phase noise is a measure (dBc/Hz) of the short-term frequency instability of the oscillator. It is measured as the