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1、翻译THE INTRODUCE OF I2C-BUS PROTOCOL1、THE I2C-BUS SPECIFICATION1.1、Here are some of the features of the I2C-bus: Only two bus lines are required; A serial data line (SDA)and a serial clock line (SCL). Each device connected to the bus is software addressable by a unique address and simple master/slave
2、 relationships exist at all times; Masters can operate as master-transmitters or as master-receivers.Its a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer.Serial, 8-bit oriented, bi-directiona
3、l data transfers can be made at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed mode.On-chip filtering rejects spikes on the bus data line to preserve data integrity The number of ICs that can be connected to the same bus is limited onl
4、y by a maximum bus capacitance of 400 pF.2、INTRODUCTION TO THE I2C-BUS SPECIFICATIONFor 8-bit oriented digital control applications, such as those requiring microcontrollers, certain design criteria can be established: A complete system usually consists of at least one microcontroller and other peri
5、pheral devices such as memories and I/O expanders The cost of connecting the various devices within the system must be minimized A system that performs a control function doesnt require high-speed data transfer Overall efficiency depends on the devices chosen and the nature of the interconnecting bu
6、s structure. To produce a system to satisfy these criteria, a serial bus structure is needed. Although serial buses dont have the throughput capability of parallel buses, they do require less wiring and fewer IC connecting pins. However, a bus is not merely an interconnecting wire, it embodies all t
7、he formats and procedures for communication within the system.Devices communicating with each other on a serial bus must have some form of protocol, which avoids all possibilities of confusion, data loss and blockage of information. Fast devices must be able to communicate with slow devices. The sys
8、tem must not be dependent on the devices connected to it, otherwise modifications or improvements would be impossible. A procedure has also to be devised to decide which device will be in control of the bus and when. And, if different devices with different clock speeds are connected to the bus, the
9、 bus clock source must be defined. All these criteria are involved in the specification of the I2C-bus.3、 THE I2C-BUS CONCEPTThe I2C-bus supports any IC fabrication process (NMOS,CMOS, bipolar). Two wires, serial data (SDA) and serial clock (SCL), carry information between the devices connected to t
10、he bus. Each device is recognized by a unique address (whether its a microcontroller, LCD driver, memory or keyboard interface) and can operate as either a transmitter or receiver, depending on the function of the device. Obviously an LCD driver is only a receiver,whereas a memory can both receive a
11、nd transmit data. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table 1). A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any
12、device addressed is considered a slave. The I2C-bus is a multi-master bus. This means that more than one device capable of controlling the bus can be connected to it. As masters are usually micro-controllers,lets consider the case of a data transfer between twomicrocontrollers connected to the I2C-b
13、us This highlights the master-slave and receiver-transmitter relationships to be found on the I2C-bus. It should be noted that these relationships are not permanent, but only depend on the direction of data transfer at that time. microcontroller A terminates the transfer. Even in this case, the mast
14、er (microcontroller A) generates the timing and terminates the transfer. The possibility of connecting more than one microcontroller to the I2C-bus means that more than one master could try to initiate a data transfer at the same time.To avoid the chaos that might ensue from such an event -an arbitr
15、ation procedure has been developed. This procedure relies on the wired-AND connection of all I2C interfaces to the I2C-bus. If two or more masters try to put information onto the bus,the first to produce a one when the other produces a zero will lose the arbitration. The clock signals during arbitra
16、tion are a synchronized combination of the clocks generated by the masters using the wired-AND connection to the SCL line Generation of clock signals on the I2C-bus is always the responsibility of master devices; each master generates its own clock signals when transferring data on the bus. Bus cloc
17、k signals from a master can only be altered when they are stretched by a slow-slave device holding-down theclock line, or by another master when arbitration occurs.4、 GENERAL CHARACTERISTICS Both SDA and SCL are bi-directional lines, connected to a positive supply voltage via a current-source or pul
18、l-up resistor. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. Data on the I2C-bus can be transferred at rates of up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the F
19、ast-mode, or up to 3.4 Mbit/s in the High-speed mode. The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF. For information onHigh-speed mode master devices, see Section 13.5、 BIT TRANSFERDue to the variety of different technology devices (CMOS,NMO
20、S, bipolar) that can be connected to the I2C-bus,the levels of the logical 0 (LOW) and 1 (HIGH) are not fixed and depend on the associated level of VDD. One clock pulse is generated for each data bit transferred.6、 TRANSFERRING DATA6.1、 Byte formatEvery byte put on the SDA line must be 8-bits long.
21、The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a slave cant receive or transmit another complete byte of data until it has performed some other function, f
22、or example servicing an internal interrupt, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.In some cases, its permitted to use a different format from the I2C-bus form
23、at (for CBUS compatible devices for example). A message which starts with such an address can be terminated by generation of a STOP condition,even during the transmission of a byte. In this case, no acknowledge is generated. 7、 ARBITRATION AND CLOCK GENERATION7.1、 SynchronizationAll masters generate
24、 their own clock on the SCL line to transfer messages on the I2C-bus. Data is only valid during the HIGH period of the clock. A defined lock is therefore needed for the bit-by-bit arbitration procedure to take place.Clock synchronization is performed using the wired-AND connection of I2C interfaces
25、to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and, once a device clock has gone LOW, it will hold the SCL line in that state until the clock HIGH state is reached. However, the LOW to HIGH transition
26、of this clock may not change the state of the SCL line if another clock is still within its LOW period. The SCL line will therefore be held LOW by the device with the longest LOW period. Devices with shorter LOW periods enter a HIGH wait-state during this time.When all devices concerned have counted
27、 off their LOW period, the clock line will be released and go HIGH. There will then be no difference between the device clocks and the state of the SCL line, and all the devices will start counting their HIGH periods. The first device to complete its HIGH period will again pull the SCL line LOW.In t
28、his way, a synchronized SCL clock is generated with its LOW period determined by the device with the longest clock LOW period, and its HIGH period determined by the one with the shortest clock HIGH period.7.2 、 ArbitrationA master may start a transfer only if the bus is free. Two or more masters may
29、 generate a START condition within the minimum hold time (tHD;STA) of the START condition which results in a defined START condition to the bus.Arbitration takes place on the SDA line, while the SCL line is at the HIGH level, in such a way that the master which transmits a HIGH level, while another
30、master is transmitting a LOW level will switch off its DATA output stage because the level on the bus doesnt correspond to its own level.Arbitration can continue for many bits. Its first stage is comparison of the address bits (addressing information is given in Sections 10 and 14). If the masters a
31、re each trying to address the same device, arbitration continues with comparison of the data-bits if they are master-transmitter,or acknowledge-bits if they are master-receiver. Because address and data information on the I2C-bus is determined by the winning master, no information is lost during the
32、 arbitration process.A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration.As an Hs-mode master has a unique 8-bit master code, it will always finish the arbitration during the first byteIf a master also incorporates a slave functio
33、n and it loses arbitration during the addressing stage, its possible that the winning master is trying to address it. The losing master must therefore switch over immediately to its slave mode.Figure 9 shows the arbitration procedure for two masters. Of course, more may be involved (depending on how
34、 many masters are connected to the bus). The moment there is a difference between the internal data level of the master generating DATA 1 and the actual level on the SDA line, its data output is switched off, which means that a HIGH output level is then connected to the bus. This will not affect the
35、 data transfer initiated by the winning master.Since control of the I2C-bus is decided solely on the address or master code and data sent by competing masters, there is no central master, nor any order of priority on the bus.Special attention must be paid if, during a serial transfer, the arbitratio
36、n procedure is still in progress at the moment when a repeated START condition or a STOP condition is transmitted to the I2C-bus. If its possible for such a situation to occur, the masters involved must send this repeated START condition or STOP condition at the same position in the format frame. In
37、 other words, arbitration isnt allowed. A repeated START condition and a data bit A STOP condition and a data bit A repeated START condition and a STOP condition.Slaves are not involved in the arbitration procedure.8、 FORMATS WITH 7-BIT ADDRESSESAfter the START condition (S), a slave address is sent
38、. This address is 7 bits long followed by an eighth bit which is a data direction bit (R/W) - a zero indicates a transmission (WRITE), a one indicates a request for data (READ). A data transfer is always terminated by a STOP condition (P) generated by the master. However, if a master still wishes to
39、 communicate on the bus, it can generate a repeated START condition (Sr) and address another slave without first generating a STOP condition. Various combinations of read/write formats are then possible within such a transfer.Possible data transfer formats are: Master-transmitter transmits to slave-
40、receiver. The transfer direction is not changed. Master reads slave immediately after first byte. At the moment of the first acknowledge, the master- transmitter becomes a master- receiver and theslave-receiver becomes a slave-transmitter. This first acknowledge is still generated by the slave. The
41、STOP condition is generated by the master, which has previously sent a not-acknowledge (A). During a change of direction within a transfer, the START condition and the slave address are both repeated, but with the R/W bit reversed. If a master receiver sends a repeated START condition, it has previo
42、usly sent a not-acknowledge (A).NOTES:1. Combined formats can be used, for example, to control a serial memory. During the first data byte, the internal memory location has to be written. After the START condition and slave address is repeated, data can be transferred.2. All decisions on auto-increm
43、ent or decrement of previously accessed memory locations etc. are taken by the designer of the device.3. Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the sequence.4. I2C-bus compatible devices must reset their bus logic on receipt of a START or repeated START c
44、ondition such that they all anticipate the sending of a slave address, even if these START conditions are not positioned according to the proper format.5. A START condition immediately followed by a STOP condition (void message) is an illegal format.I2C 总线协议简介1、I2C总线规范1.1、 I2C 总线的特征 只要求两条总线线路一条串行数据线
45、SDA 一条串行时钟线SCL。 每个连接到总线的器件都可以通过唯一的地址和一直存在的简单的主机从机关系软件设定地址主机可以作为主机发送器或主机接收器。 它是一个真正的多主机总线如果两个或更多主机同时初始化数据传输可以通过冲突检测和仲裁防止数据被破坏。 串行的8 位双向数据传输位速率在标准模式下可达100kbit/s 快速模式下可达400kbit/s 高速模式下可达3.4Mbit/s。 片上的滤波器可以滤去总线数据线上的毛刺波保证数据完整。 连接到相同总线的IC器件数量只受到总线的最大电容400pF 限制。2、介绍I2C总线规范对于面向8 位的数字控制应用譬如那些要求用微控制器的要建立一些设计标
46、准： 一个完整的系统通常由至少一个微控制器和其他外围器件例如存储器和I/O 扩展器组成。 系统中不同器件的连接成本必须最小。 执行控制功能的系统不要求高速的数据传输。 总的效益由选择的器件和互连总线结构的种类决定。产生一个满足这些标准的系统需要一个串行的总线结构，尽管串行总线没有并行总线的数据吞吐能力，但它们只要很少的配线和IC连接管脚。然而总线不仅仅是互连的线，还包含系统通讯的所有格式和过程。串行总线的器件间通讯必须有某种形式的协议避免所有混乱数据丢失和妨碍信息的可能性。快速器件必须可以和慢速器件通讯。系统必须不能基于所连接的器件，否则不可能进行修改或改进应当设计一个过程决定哪些器件何时可以
47、控制总线。而且，如果有不同时钟速度的器件连接到总线必须定义总线的时钟源。所有这些标准都在I2C 总线的规范中。3、I2C 总线的概念I2C 总线支持任何IC 生产过程（NMOS、CMOS、双极性）两线串行数据（SDA） 和串行时钟（SCL）线在连接到总线的器件间传递信息。每个器件都有一个唯一的地址识别（无论是微控制器、LCD驱动器、存储器或键盘接口），而且都可以作为一个发送器或接收器9由器件的功能决定。很明显，LCD驱动器只是一个接收器，而存储器则既可以接收又可以发送数据。除了发送器和接收器外器件在执行数据传输时也可以被看作是主机或从机。 主机是初始化总线的数据传输并产生允许传输的时钟信号的器
48、件。此时，任何被寻址的器件都被认为是从机。I2C 总线是一个多主机的总线。这就是说，可以连接多于一个能控制总线的器件到总线。由于主机通常是微控制器，让我们考虑以下数据在两个连接到I2C 总线的微控制器之间传输的情况。这突出了I2C 总线的主机从机和接收器发送器的关系。应当注意的是：这些关系不是持久的，只由当时数据传输的方向决定。 微控制器A 终止传输，甚至在这种情况下主机（微控制器A）也产生定时而且终止传输。连接多于一个微控制器到I2C 总线的可能性意味着超过一个主机可以同时尝试初始化传输数据。为了避免由此产生混乱，发展出一个仲裁过程，它依靠线与连接所有I2C 总线接口到I2C 总线。 如果两
49、个或多个主机尝试发送信息到总线，在其他主机都产生0 的情况下首先产生一个1 的主机将丢失仲裁。仲裁时的时钟信号是用线与连接到SCL 线的主机产生的时钟的同步结合。在I2C 总线上产生时钟信号通常是主机器件的责任：当在总线上传输数据时，每个主机产生自己的时钟信号。主机发出的总线时钟信号只有在以下的情况才能被改变：慢速的从机器件控制时钟线并延长时钟信号，或者在发生仲裁时被另一个主机改变。4、总体特征 SDA 和SCL 都是双向线路，都通过一个电流源或上拉电阻连接到正的电源电压。当总线空闲时，这两条线路都是高电平，连接到总线的器件输出级必须是漏极开路或集电极开路才能执行线与的功能。I2C 总线上数据的传输速率在标准模式下可达100kbit/s，在快速模式下可达40