《CMOS4046集成电路研究锁相环（PLL）的工作原理毕业论文外文翻译.docx》由会员分享，可在线阅读，更多相关《CMOS4046集成电路研究锁相环（PLL）的工作原理毕业论文外文翻译.docx（9页珍藏版）》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。
1、本实验要使用CMOS4046集成电路研究锁相环（PLL）的工作原理。电路包括两个不同的鉴相器和一个VCO。另外还有一个齐纳二极管参考电压源用在供电调节中，在解调器输出中有一个缓冲电路。用户必须提供环路滤波器。4046具有高输入阻抗和低输出阻抗，容易选择外围元件。注意事项1. 本实验较为复杂，进入实验室之前，确认你已经弄懂了电路预计应该怎样工作。对 某样东西还没有充分分析之前，不要去尝试制作它。在开始实验之前要通读本文。2. 在实验第一部分得到的数据要用来完成实验的其它任务。所以要仔细对待这部分内容。3. 小心操作4046芯片，CMOS集成电路很容易损坏。避免静电释放，使用10k电阻 把信号发生
2、器的输出耦合到PLL。在关掉4046供电电源之前先关闭信号发生器，或者从信号输入端给整个电路供电。要避免将输出端对电源或对地短路，TTL门电 路可以容忍这种误操作但CMOS不能（要注意松散的导线）。CMOS输出也没有能力驱动电容负载。VSS应该接地，VDD应该接5V，引脚5应该接地（否则VCO被禁止）。1 VCO工作原理 阅读数据手册中的电路描述。VCO常数（单位为弧度/秒-伏）是工作频率变化与输入电压（引脚9上）变化之比值。测量出，即，画出输出频率关于输入电压的曲线。确认数据范围要覆盖5kHz到50kHz。对于R1, R2 和C的各种参数取值进行测量，确定对于R1 ,R2 和C 是怎样的近似
3、关系。测量VCO输出的上升和下降时间，研究电容性负载的影响。2 无源环路滤波器无源环路滤波器位于鉴相器输出与VCO输入之间。此滤波器对鉴相器输出中的高次谐波进行衰减，并控制环路的强度。通常用一个简单RC滤波器就可以满足要求，这种设计能避免有源滤波器设计中固有的电平移动和输出限制的恼人问题。但另外一方面，有源滤波器可以提供更优越的性能。2.1 相位比较器 首先来看一下4046的相位比较器II的输出。该输出端是一个三态器件，这可以在环路锁定时减小波纹。与存在两倍基频拍频的情况不同，这里没有任何拍频。糟糕的方面是，当我们需要为环路建立一个框图时，却不能很好地定义。当向上或向下驱动之一接通时，输出端表
4、现为电压源。但是当输出端悬浮时，它实质上为一个电流源（一个0A电流源）。 因此的值将依赖于给定的滤波器。考察图1。 图1 相位比较器II的输出 图中当向上驱动器接通时，相位比较器输出为，当向下驱动器接通时，当相位比较器处在开路状态时， 。我们可以求出输出的平均值： 注意的值依赖于 的值。这使得环路的计算非常困难。实际上，当不是2.5V时，对于正的或负的相位误差，的值不相同。为了得到可用的输出，我们可以修改输出端来产生一个固定的值。为此，我们可以加上一个有源元件，使得当输出端开路时 的值确定。在图2和图4中，开路值都定义为2.5V，结果是对于正的和负的都有相等的值。如果你准备给相位比较器II仅仅
5、搭配一个RC网络，一定要明白这样的方案在锁定范围的极端情况下，环路的动态特性会显著地降低。 使用无源环路滤波器的简单二阶PLL如图2所示。其中使用了相位比较器II。当环路锁定时，鉴相器输出电压平均值为。增量鉴相器增益常数弧度。考虑下面指标： 其中我们定义了中心频率f0作为当引脚9为.5V电压时VCO的输出频率。请使用图2给出的结构来设计并制作一个电路实现上述指标。 将你的设计写成文档，内容包括框图以及环路传递函数的幅度、相位波特图。讨论的问题：稳态相位误差和锁定范围如何？预期结果与实际测量结果的比较。 环路的相位裕度可以从环路阶跃响应的测量中导出。一种方法是在输入端施加一个调频信号并观察解调输
6、出。具体步骤是，在产生输入信号的函数信号发生器上，用方波调制其频率。观察VCO输入电压，测量其上升时间和尖峰过冲，研究这些测量结果是否与给定转折频率和相位裕度的二阶系统相符合？注意：频偏应该很小，避免PLL失锁。 图3 滞后环路滤波器在图3中，环路滤波器用一个滞后网络代替。这个网络允许单独设定和。因而环路可以有宽的锁定范围（由确定）和窄的带宽。请设计并制作满足如下指标的电路：设计文档中要包括必要的波特图。 滞后滤波器对于来自鉴相器的高频波纹不能提供很大的衰减。当你观察VCO输入端（引脚9）的电压时可以看得很清楚。在R4两端跨接一个电容来增加对高频的衰减。如果引起的极点位于转折频率之外，则除了高
7、频段的锯齿被去掉之外，引起的FM阶跃响应的变化可以如果没有可用的频率信号发生器，可以考虑使用另外一个4046的VCO 。被忽略。 现在尝试增加频偏，让环路失锁，注意相位比较器输出端和VCO输入端的响应。2.2 异或鉴相器 现在考虑，如果用相位比较器I（一个异或门）替换2.1节中描述的滞后补偿PLL中的相位比较器II会怎样？你应该能从理论和实验两方面回答这个问题。具体问题包括，鉴相器增益、环路带宽、相位裕度、稳态相位误差、锁定范围和（实验中）取得锁定的难易程度如何？ 注意：如果达到锁定有困难，尝试放慢输入频率扫描速度，直到电路锁定。这个电路是否锁定在谐波上？电路对占空比是否敏感？3 有源滤波器回
8、到2.1节中描述的使用相位比较器II的滞后补偿PLL。像前面一样施加FM调制输入观察阶跃响应。观察相位比较器的输出（引脚13）。如果用视觉将高频成分平均掉，稳态响应相位误差和动态跟踪误差应该很明显看出 4 。尝试改变输入频率范围。有源滤波器用来减低这个跟踪误差。一种可能的有源滤波器PLL实现如图4所示。 图4 有源环路滤波器 在使用这种滤波器时要防范一些问题。运算放大器很容易产生出导致4046烧毁的电压。因此，如图用二极管对PLL输入进行钳位是一种好的做法。低通滤波器（R3和C2）对鉴相器的高频波纹提供进一步滤波。还要注意防止运算放大器进入摆率（slew rate）限制范围。 这里有源电路仍然
9、确定了鉴相器II的开路状态输出为2.5V。反相器是必要的，因为PLL需要一个同相结构。R4C1确定转折频率。R2确定零点位置，因而确定了稳定性。1/( R3 C2) 应该设定在的5倍以上。与前面相同（对于设定鉴相器开路状态电压为2.5V的任何环路 注：如果觉得视觉平均不够满意，采用RC=0.1ms的简单RC滤波器过滤vD将可以得到相位误差平均值的波形。为避免给相位比较器加上低阻抗负载，要使用一个大阻值电阻（1M即可）。重要提示：此滤波器并不在环路中，它位于相位比较器输出与示波器之间。滤波器来说都如此）。如果愿意，你可以任意设计自己的二阶环路滤波器结构，只是要注意不要毁坏4046芯片。请用有源环
10、路滤波器设计并制作一个满足如下指标的PLL电路：画出适当的波特图。完成阶跃响应测量。同以前一样观察鉴相器输出（引脚13）。对于动态跟踪误差和稳态误差进行讨论。4 线性鉴相器与频率合成 现在考虑尝试锁定到多个信号的复合体中的一个信号上的问题。复合信号的过零点不一定与要锁定信号的过零点一致。因此，使用过零点敏感的鉴相器，例如相位比较器II，甚至于异或门，都是不可行的。 我们希望利用一个线性鉴相器，它能实现复合信号与VCO输出的模拟相乘。由于VCO输出为方波（一系列1和负1），我们可以将要求放宽到需要一个乘法器，它能把输入复合信号与1或-1相乘，且产生的失真最小。 考察图5中的电路。其中鉴相器的是多
11、少？对于零输出其稳态相位误差如何？(图5 线性鉴相器)注意将依赖于输入信号的幅度。在本实验的余下部分我们假定要锁定信号的幅度为300mV峰-峰值。 现在还要考虑需要两倍于输入频率的VCO输出频率的问题。如图6所示，在反馈路径中加入一个除2模块，闭合环路系统将能实现乘2功能。设计并制作满足如下指标的电路：注意对于频率乘法系统“零稳态相位误差”并没有严格定义。为了我们的目的，将 “零稳态相位误差”定义为输入和输出两者的正向过渡相吻合。在你的PLL反馈路径上用D触发器（73LS74）实现除2模块。确认在环路分析中包含其作用。注意，若鉴相器存在稳态相位偏移，可以在除2模块中对此进行补偿。将D触发器的输
12、入和输出与适当的反相器网络和异或门混合起来可以实现和90180的相移。画出适当的波特图。完成阶跃响应测量。同以前一样观察鉴相器输出（引脚13）。对于动态跟踪误差和稳态误差进行讨论。In this lab you will investigate phase lock loop (PLL) operation using the CMOS 4046 integrated circuit. It contains two different phase detectors and a VCO. It also includes a zener diode reference for power s
13、upply regulation and a buffer for the demodulator output. The user must supply the loop filter. The high input impedances and low output impedances of the 4046 make it easy to select external components.Notes1. This lab is complicated. Be sure that you understand how the circuits are supposed to wor
14、k before coming into the lab. Do not try to build something that you have not fully analyzed. Read this entire assignment before beginning to work on it.2. Data taken in Part 1 will be needed in order to complete your designs in the rest of the lab, therefore, do this part carefully.3. Handle the 40
15、46 with care. CMOS integrated circuits are easily destroyed. Avoid static discharges. Use a 10k resistor to couple the signal generator to the PLL. Turn of the signal generator before turning off power to the 4046, or else you will power up the entire circuit from the signal input. Avoid shorting th
16、e outputs to ground or the supply. A TTL gate can withstand this kind of abuse, but CMOS cannot (be careful of loose wires). CMOS does not have the output strength to drive capacitive loads. VSS should be connected to ground, VDD should be connected to 5V, and pin 5 should be connected to ground (ot
17、herwise the VCO in inhibited).1 VCO OperationRead the circuit description in the datasheet. The VCO constant ( in radians/sec-volt) is the ratio of the change in operating frequency to the change in input voltage (on pin 9). Measure , that is, graph the output frequency versus the input voltage. Be
18、sure that your data covers the range from 5 kHz to 50 kHz. Make the measurements with various values1 of R1, R2, and C. Approximately, how is related to R1, R2, and C? Measure the rise and fall times of the VCO output. Investigate the effects of capacitive loading.2 Passive Loop FiltersThe loop filt
19、er is placed between the phase detector output and the VCO input. This filter attenuates the high frequency harmonics present in the phase detector output. It also controls loop dynamics. Often a simple RC filter will function adequately. These designs avoid embarassing level shifting and output lim
20、iting problems inherent in active filter designs. On the other hand, active filters may offer superior performance.2.1 Phase Comparator IIBefore continuing, consider the output of phase comparator II of the 4046. The output is a tristate device. This causes a reduction of the ripple when the loop is
21、 locked. Instead of a 50% duty cycle beat note at twice the fundamental, there is no beat note at all. Unfortunately, when one wishes to construct a block diagram for the loop, is not well-specified. When either the upper or lower driver is on, the output looks like a voltage source, but when the ou
22、tput is floating, it is essentially a current source (a source of 0 amps). Therefore the value of will depend on the specific filter. Consider Figure 1.Figure 1: Phase comparator II outputSo the phase comparator output iswhen the upper driver is on, when the lower driver is on, and when the phase co
23、mparator is in the open state. We can find the average value of the output: Note that the value of KD depends on the value of . This makes the mathematics of the loop much more confusing. In fact is different for positive and negative phase errors when 、is not 2.5 volts. In order to get a usable out
24、put, we can modify the output to yield a fixed value of . To do this we can put an active element in to define the value of when the output is open. In both Figures 2 and 4 the open value is defined as 2.5 volts which leads to an equal value of for positive and negative e. If you use phase comparato
25、r II with just an RC network, be sure to realize that the loop dynamics may be considerably compromised at extremes of lock range. A simple second order PLL with “passive” loop filter is illustrated in Figure 2. Phase comparator II is used. When the loop is locked, the average phase detector output
26、voltage is volts. The incremental phase detector gain constant is then volts/radian. Consider the following specifications:Figure 2: “Passive” loop filterWhere we define the center frequency, fo, as the VCO output frequency when pin 9 is 2.5 volts. Using the topology illustrated in Figure 2, design
27、and build a circuit that meets these specifications。Document your design with block diagrams and Bode plots of the magnitude and angle of the loop transmission. What is the steady state phase error and lock range? How do your predictions and measurements compare? The phase margin of the loop may be
28、deduced from measurements of the step response of the loop. One technique is to apply a FM signal to the input and look at the demodulated output. Specifically, use a square wave to modulate the frequency of the function generator which you are using for your input3.Observe the VCO input voltage. Me
29、asure the risetime and peak overshooot. Are these results compatible with a second order system with the specified crossover frequency and phase margin? NOTE: the frequency deviation should be very small so that the PLL does not break lock.Figure 3: Lag loop filterThe loop filter is replaced by the
30、lag network illustrated in Figure 3. It will allow you to set KO and !c independently. Hence, the loop may have a wide lock range (as determined by KO) and a narrow bandwidth. Design and build a circuit to meet the following specifications:Include the appropriate Bode plots. The lag filter does not
31、provide much attenuation of the high frequency ripple from the phase detector. This is evident when you observe the voltage at the VCO input (pin 9). Place a capacitor across R4 in order to increase the high frequency attenuation. If this pole is placed beyond the loop crossover frequency, there wil
32、l be negligible change in the FM step response, except that the high frequency teeth will be removed. Now try increasing the FM frequency deviation so that the loop breaks lock. Note the response at the phase comparator output and VCO input.2.2 XOR Phase DetectorWhat happens if you substitute phase
33、comparator I (an exclusive-or gate) for phase comparator II in the lag compensated PLL described in Part 2.1? You should be able to answer this question theoretically and experimentally. Specifically, what is the phase detector gain , the loop bandwidth, the phase margin, the steady state phase erro
34、r, the lock range, and the ease of acquiring lock (experimentally)?Note: if you have difficulty in acquiring lock, try slowly scanning the input frequency until the circuit locks. Will this circuit lock on harmonics? Is the circuit duty cycle sensitive?3 Active FiltersReturn to the lag compensated P
35、LL using phase comparator II as in Part 2.1. Apply a FM modulated input to observe the step response as before. Look at the output of the phase comparator (pin 13). The steady state phase error and dynamic tracking error should be apparent if you mentally average out the high frequency components4.
36、Try varying the input frequency range.Active filters are used to reduce this tracking error. A possible active filter PLL realization is illustrated in Figure 4. Certain precautions must be taken when such filters are used. The opamp can easily supply voltages to the 4046 that will burn it out. For
37、this reason, it is a good idea to diode clamp the inputs to the PLL as shown. The low pass filter (R3 and C2) provides extra attenuation of the high frequency phase detector ripple. It also should keep the opamp from slew rate limiting. Again the active circuit specifies the open state output of pha
38、se detector II to be 2.5 volts. The inverter is necessary because the PLL wants a non-inverting topology. R4C1 sets the crossover frequency, and R2 sets the zero location, hence the stability. 1=(R3C2) should be set at least a factor of 5 above. is the same as before (as it would be for any loop fil
39、ter which specified the open state volatage of the phase detector as 2.5 volts).Feel free to design your own second order loop filter topology if you wish, just be careful not to destroy the 4046. Design and build a PLL using an active loop filter to meet the following specifications:Note: If you fi
40、nd mental averaging unsatisfying, filtering with a simple passive RC filter with RC =0:1 ms will give you a picture of the average value of the phase error. To avoid loading the phase comparator with a low impedance, make the resistor R a large value (1M is fine). IMPORTANT: this filter is not in th
41、e loop, it is between the phase comparator output and the scope.Draw the appropriate Bode plots. Make measurements of the step response. Again look at the phase detector output (pin 13). What can you say about the dynamic tracking error? What about the steady state error?4 Linear Phase Detectors and
42、 Frequency SynthesisConsider the problem of trying to lock onto a signal in a composite mix of signals. The zero crossings of the composite signal may not coincide with the zero crossings of the signal you wish to lock to, thus the use of zero crossing sensitive phase detectors, such phase comparato
43、r II, or even XORs, is impossible.We wish to use a linear phase detector that implements an analog multiplication of the composite signal and the VCO output. Since the VCO output is a square wave (a series of ones and minusones) we can relax our requirement to needing a multiplier that can multiply
44、the incoming composite signal by either 1 or 1 with minimal distortion.Figure 5: Linear Phase DetectorConsider the circuit in Figure 5. What is for this phase detector? What will be the steady-state phase error for a zero output?Note that will depend on the amplitude of the incoming signal. For the
45、rest of this lab, assume that the signal that we wish to lock to has an amplitude of 300 mV peak-to-peak.Now, also consider the problem of wanting a VCO output frequency that is twice the input frequency. By putting a divide-by-two block in the feedback path as in Figure 6, the closed loop system sh
46、ould implement a multiply-by-two function.Figure 6: Multiply-by-two PLLDesign and build a circuit to meet the following specifications:Note that zero steady state phase error is not well defined for a frequency multiplier system. For our purposes, we define “zero steady state phase error” to be when
47、 the positive going transistions of both the input and output coincide. Using a D-flipflop (74LS74) implement a divide-by-two block in the feedback path of your PLL. Be sure to include its effects in your loop analysis. Note that if the phase detector has a steady state phase offset, you can compens
48、ate for this in your divide-by two block. Phase shifts of or can be accomplished by mixing the input and output of the D-flipfiop with the appropriate network of inverters and XOR gates.Draw the appropriate Bode plots. Make measurements of the step response. Again look at the phase detector output (pin 13). What can you say about the dynamic tracking error? What about the steady state error?