半导体制程ppt课件.ppt

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1、Outline1. Introduction2. Integrated Circuit and Its Application3. How is IC made? 一种相移振荡器一种相移振荡器 （1.3 MHz) Ge 衬底，晶体管及电阻、电容全部由衬底，晶体管及电阻、电容全部由Ge制成制成 (面积约面积约11.1x1.6mm2) 扩散工艺形成晶体管扩散工艺形成晶体管 黑蜡掩蔽腐蚀形成黑蜡掩蔽腐蚀形成Tr台面结构台面结构 用细导线互连用细导线互连证明半导体材料不仅可用于制造分证明半导体材料不仅可用于制造分立器件，而且可以制造整个电子电立器件，而且可以制造整个电子电路路1958.9.12 J.

2、Kilby 研制成功第一个半研制成功第一个半导体集成电路导体集成电路 -“Solid Circuit”J. Kilby的发明的发明“固体电路固体电路”Kilby和他和他1958,7,24的设计的设计Migration of Electronics Manufacturing From inception, electronic manufacturing has migrated geographically from the West to the East: from the US and Europe, over to Japan, through the Taiwan area, Ko

3、rea, arriving in the East: China and India.The shift in wafer production typically lags behind the rest of the supply chain, but China and India are now at the forefront of IC production!231232000 WW IC Market China6% WW MarketOthers$57.80Japan $37.80U.S.A $57.90$9.8021% WW Market2005 WW IC Market $

4、40.80Others $82.10U.S.A$36.50Japan$33.00China2006 WW IC Market 26% WW MarketOthers$87.44U.S.A$46.56$62.35Japan$57.05ChinaUS$billionSource: IC insights January 2007 In 2005, Chinas IC consumption reached USD$40.8 billion, overtaking the top spot as the worlds largest regional IC market for the first

5、time. By 2010, Chinas IC market is estimated to reach USD$124 billion in terms of overall consumption.China Becomes Worlds Largest IC MarketA Leading Foundry In The WorldSMIC BeijingSMIC ShanghaiSMIC TianjinTianjinBeijingShanghaiWuhanChengduShenzhenSMIC Assembly & Testing (Chengdu)SMIC BeijingWuhan

6、Xinxin* Chengdu Cension*提供提供0.35-0.09微米的制程技术微米的制程技术 IC Industry Business UnitIDM(Integrated Device Manufacturer)qProduct design & sales, qFabq &/or IC assemblyFab liteqProduct design & Sales, qHas Fab, but manufacture less than 50% productFablessqProduct & sales only, no Fab & assembly houseFoundryq

7、Fab onlyqNo product一条龙的集成代工服务一条龙的集成代工服务Dedicated Full Service ProviderDesignServicesMask Making WaferManufacturingWafer ProbingAssembly & Final TestWafer BumpingSOPPLCCTSOPQFPBGABGAFlip ChipCSP2008-IC 技技术现术现状状Integration of 108 1010 transistors in a chip.Clock frequency of more than 3GHz.Cutoff freq

8、uency of 350 GHz for SiGe bipolar.Mass production 90nmAdvanced manufacturing 65nmManufacturing development 45nmProcess and device R&D 32nm.Smallest transistor realized-5nmMOSFETOutline1. Introduction2. Integrated Circuit and Its Application3. How is IC made?导体导体半导体半导体绝缘体绝缘体 q 半导体材料特性半导体材料特性: 经经掺杂后掺杂

9、后，可藉由，可藉由电场电场(电压电压)、光光、温度温度、压力压力、磁场等磁场等改变或控制其导电特性。改变或控制其导电特性。q 最广为应用的集成电路芯片材料：最广为应用的集成电路芯片材料： 硅硅 (Silicon, Si)。纯硅导电特性差，纯硅导电特性差， 可藉掺杂可藉掺杂(Doping, 将杂质加入硅片中将杂质加入硅片中)改变或控制改变或控制其导电特性。其导电特性。 如何掺杂及控制杂质在硅片中分如何掺杂及控制杂质在硅片中分布是半导体重要制程技术之一布是半导体重要制程技术之一 。半导体半导体 Semiconductor分离分离式式电电路路 Discrete CircuitITANIUM MICR

10、OPROCESSOR( 1.72 Billion Transistors 90nm 595 mm2)To make wafers, polycrystalline silicon is melted. The melted silicon is used to grow silicon crystals (or ingots) that are sliced into wafers.首先融化多晶硅，生成晶柱，然后切割成晶圆。Raw Material for WafersA slice of semiconductor material, processed to have specified

11、electrical characteristics, especially before it is developed into an electronic component or integrated circuit. 晶圆上的小颗粒，经过处理后具有特殊电性用途。Semiconductor Glossary 半导体术语表 Die 晶粒Assembled semiconductor electronic component.切割封装好的半导体电子元件。Chip 晶片、芯片A small, thin, circular slice of a semiconductor material,

12、such as Silicon, on which repeated integrated circuits can be formed.半导体物质(如纯硅)小薄圆片，在上面可以形成一个个完整电路Wafer 晶圆Silicon Technology 矽矽(硅硅)技术技术6 吋吋 (15.24cm)8 吋吋 (20.32cm)12 吋吋 (30.48cm)1.78 倍倍 2.25 倍倍 (A) Production Capability (生产生产能力能力)(B) Design Capability (设计设计能力能力)元件縮小元件縮小0.18 um (微米微米)0.13 um (微米微米)1

13、um (微米微米) = 百万分之一米（m)= 头发的 分之一头发头发的的 分之一分之一千万万芯片分类及应用Types of ICs & Applications应用领域Applications应用领域应用领域应用领域Some types of ICs芯片分类芯片分类DRAM动态随机存储器MPUs微处理器Computer电脑ASIC特定用途集成电路DSPs数字信号处理器Consumer消费Flash闪存存储器 EEPROMs电可擦除只读存储器Communi-cation通讯Electronic PackageFirst level package(Single-chip module)First

14、 level package(Multi-chip module)Second level package(PCB or card)Third level package(Mother board)Outline1. Introduction2. Integrated Circuit and Its Application3. How is IC made?Building an IC ChipTape-out (used to be a lot of informationput on tape)Like a blueprint for wafer productionHierarchy o

15、f IC ChipMultilevel MetallizationM1ContactVia 1M2Via 2M3Via 3M4IMD3ILDIMD1IMD2Backend processFrontendActiveAreaDiffusion Barrier/Adhesion PromoterPlug电晶体电晶体 (晶体管晶体管) MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor连接线连接线晶圆芯片制作概述Wafer Manufacturing Overview晶柱晶柱Silicon Ingot芯片芯片Wafer光罩制作光罩制作/

16、光刻光刻离子植入离子植入切割、封装切割、封装电镀电镀(Die,晶粒)(Chip,晶芯)蚀刻蚀刻Mask Making/ PhotolithographyIon ImplantationAssembly&TestingElectroplatingEtching沉积沉积Deposition PHOTO (黃光黃光) Module Process Procedures (制程步骤制程步骤):(a) PR_coating (上光上光 阻阻) 光阻光阻见见白光即白光即反应反应 用用黄光黄光 (b) Photo_mask & exposure (上光罩及上光罩及曝光曝光)(c) CD measuremen

17、t (曝光曝光后量测后量测) 简称简称 ADI_CD(d) After Develop Inspection (曝光后检查曝光后检查 ) 简称简称 ADIPR: Photo Resist (光光 阻阻)(化学物品)CD: Critical Dimension(重要尺寸重要尺寸)Mask (光罩光罩)特殊特殊光线光线曝光曝光区区光光 阻阻光光 阻阻光光 阻阻(1) 大小或宽度是否OK ?(ADI_CD)(2) 光阻是否曝开 ? (ADI) PHOTO (黄光黄光) Module 光阻光阻区区 (PR)ADI_CDADI_CD光光阻阻区区(PR) ETCH (蚀刻蚀刻) Module Proces

18、s Procedures (制程步骤制程步骤):(a) Dry Etching (气相蚀刻气相蚀刻) 化化学反应后成气体去除学反应后成气体去除(b) WET_PR_stripping (光阻去除光阻去除, 硫硫酸槽酸槽) (c) CD measurement (蚀刻后蚀刻后量測量測) 简称简称AEI_CD(d) After Etch Inspection (蚀刻后检查蚀刻后检查) 简称简称 AEI光光 阻阻光光 阻阻Etching gas(蚀刻气体蚀刻气体)光阻去除光阻去除(WET)大小或宽度是否OK ?(AEI_CD)光阻同光阻同时会被吃掉一些时会被吃掉一些 Thin-Film (薄膜薄膜)

19、 Module Process Procedures (制程步骤制程步骤):(a) Thin film deposition (薄膜薄膜沉积沉积, 单单片片)(b) Thickness measurement (沉积沉积厚度厚度量測量測)(c)Film types (薄膜薄膜种类种类):(i) 非导体非导体: oxide (氧化物氧化物), nitride (氮化硅氮化硅)(ii) 导体导体: metal (金属金属: W, Ti, TiN, Al)Si3N4 (氮化硅氮化硅)SiH4 (气气) + NH3 (气气) Si3N4 (固固)TiCl4 (气气) + NH3(气气) TiN (固固

20、)厚度符合厚度符合要求要求 ? CMP (化学机械研磨化学机械研磨) Module Process Procedures (制程步骤制程步骤):(a) Chemical Mechanical Polishing (化学机械研磨化学机械研磨) 简称简称 CMP(b) 单片研磨单片研磨(c) 主要目的主要目的: 表面表面平坦化平坦化(d) Thickness measurement (研磨后研磨后厚度厚度量測量測)FilmCMP平坦化平坦化厚度符合厚度符合要求要求 ? Diffusion (扩散扩散) Module Process Procedures (制程步骤制程步骤):(a) Film de

21、position (炉管薄膜沉积炉管薄膜沉积, 150片片)(b) Thickness measurement (沉积沉积厚度厚度量測量測)(c)Film types (薄膜薄膜种类种类):(i) 非导体非导体: oxide (氧化物氧化物), nitride (氮化硅氮化硅)(ii) 导体导体: Doped-poly & WSiFilmSi (固固) + O2 (气气) SiO2 (固固)SiH4 (气气) + NH3 (气气) Si3N4 (固固)厚度符合厚度符合要求要求 ? WET (酸槽酸槽) Module Process Procedures (制程步骤制程步骤):(a) Pre-c

22、lean for deposition (薄膜薄膜沉积沉积前清洗前清洗)(b) Film removal by WET (薄膜去除薄膜去除)(c) PR strip (光阻去除光阻去除)酸槽浸泡酸槽浸泡Surface clean(表面清洗表面清洗)Film depositionFilm removal薄膜薄膜 或或 扩散扩散 制程制程光阻光阻去除去除 或或磷酸吃磷酸吃 Si3N4 Implant (离子植入离子植入) Module Process Procedures (制程步骤制程步骤):(a) Photo Exposure (黄光黄光曝光曝光)(b) Ion Implantation (离

23、子植入离子植入) 简称简称 IMP(c) WET_PR_stripping (光阻去除光阻去除, 酸槽酸槽) Mask (光罩光罩)特殊特殊光线光线曝光曝光区区光光 阻阻光光 阻阻P+P+P+P+P+P+ P+植入区植入区光阻去除光阻去除后后 (WET) PHOTO (黄光) 制程制程 & 设备设备 ETCH (蚀刻) 制程制程 & 设备设备 Thin-Film (薄膜)-CVD 制程制程 & 设备设备 Thin-Film (薄膜)-PVD 制程制程 & 设备设备 CMP (化学机械研磨) 制程制程 & 设备设备 Diffusion (扩散) 制程制程 & 设备设备 WET (酸槽) 制程制程

24、 & 设备设备 Implant (离子植入) 制程制程 & 设备设备 Integration (制程整合) Manufacture (制造部)半导体制造半导体制造工程工程Brief Process Flow - IsolationP-sub(Silicon wafer)SiN (Nitride)Pad oxide1.1. Wafer Start1.2. PAD Oxidation 110A (stress buffer)1.7. SiN (Nitride) Deposition 1.5KA1.8. Diffusion Lithography :1.8.1 P.R. coating1.8.2 S

25、tepper Exposure1.8.3 DevelopmentPhoto Resistor coatingDiffusion maskStepper ExposureDiffusion P.R.P-sub(Silicon wafer)SiN (Nitride)Pad oxideDiffusion P.R.P-sub(Silicon wafer)SiN (Nitride)Pad oxideSTISTIBrief Process Flow Isolation (Cont)1.7. Trench (STI) Plasma Etching1.7.1 SiN Etching1.7.2 Silicon

26、Etching1.8. Photo Resistor removeSEM (Scanning Electronic Microscope)Brief Process Flow Isolation (Cont)1.7. APCVD STI refill 1.7.1 Liner Oxide Growth1.7.2 APCVD Oxide deposition1.7.3 STI Furnace 1000C Densify1.8. STI CMP (Chemical-Mechanical Polish)1.9. SiN removeDiffusion P.R.P-sub(Silicon wafer)S

27、iN (Nitrid)Pad oxideSTISTISTIN-WELL MaskBrief Process Flow - Well formationP.R. CoatingN-WELL P.R.Stepper Exposure2.1 N-WELL Formation :2.1.1 N-WELL PR coating2.1.2 N-WELL Lithography2.1.3 Development2.1.4 N-WELL implant2.1.5 PR stripping2.2 P-WELL Formation :2.2.1 P-WELL PR coating2.2.2 P-WELL Lith

28、ography2.2.3 Development2.2.4 P-WELL implant2.2.5 PR strippingP-sub(Silicon)Sac. oxideSTIPWELL N-WELLP.R. CoatingP-WELL MaskN-WELL Implant1. N-WELL- 12. N-WELL- 27. P MOS - VT8. P MOS anti-punchP-WELL Implant1. P-WELL- 12. P-WELL- 27. N MOS - VT8. N MOS anti-punchBrief Process Flow - Gate Oxide and

29、POLYPR coatingP-sub (Silicon)NWELLPWELLGate OxideTG MaskStepper ExposureGate Oxide 2UPOLY growth3 Gate Oxide Formation :3.1 Thick Gate Oxide Growth3.2 PR coating3.3 TG Lithography3.4 Development3.5 RCA-A Wet etching3.6 PR stripping3.7 Thin Gate Oxide Growth4. Poly Growth4.1 undope. POLY growth4.2 N+

30、POLY PR coating4.3 N+POLY Lithography4.4 Development4.5 N+POLY implant and PR StripPR CoatingN+POLY MaskN+POLY PRN+POLY implantTEM (Transmission Electron Microscope)Brief Process Flow - Gate EngineeringP-subNWELLSTIPWELLPolyPR coatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN-LDD Implant

31、P-LDD implant5 Poly Gate Formation :5.1 Poly annealing5.2 PR coating5.3 POLY Lithography5.4 Development5.5 POLY Gate etching5.6 PR stripping5.7 Thin Oxide Growth6. LDD (Light Dope Drain) implant6.1 N-LDD Lithography (ellipsis)6.2 NLDD / N-PKT implant6.3 P-LDD Lithography (ellipsis)6.4 PLDD / P-PKT i

32、mplantBrief Process Flow - Drain EngineeringP-subNWELLSTIPWELLPolyPR coatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN+ PRN+N+P+ PRP+P+ ImplantN+ implantGate OxideUMC.Fab8B. Generic 0.25um logic Ti-Salicide ProcessPolyTiSi2SpacerSourceDrainChannel Length7 Spacer Formation :7.1 PETEOS dep

33、.7.2 SiN dep.7.3 Spacer dry etch8. Source and Drain Formation: 8.1 N+ Lithography8.2 N+ implant8.3 PR stripping 8.4 P+ Lithography8.5 P+ implant8.6 PR strippingBrief Process Flow - ILD PassivationP-subNWELLSTIPWELLPolyPR coatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN+ PRN+N+P+ PRP+SAB

34、PSGUSG9. Salicide Formation :9.1 PETEOS-500A Cap Oxide dep.9.2 SAB (Salicide-Block) Lithography (ellipsis)9.3 Ti/Co sputtering9.4 Salicidation RTP C49 annealing9.5 TiN residual Semitool wet clean9.6 Salicidation RTP C54 annealing10. ILD Passivation10.1 SiN 300A deposition(Moisture and sodium block)1

35、0.2 AP-USG deposition(Gap filling and B,P trap)10.3 TEOS-BPSG-14K deposition(re-flow and planarization)10.4 ILD CMPP-subNWELLSTIPWELLPolyPR coatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN+ PRN+N+P+ PRP+SABPSGUSGPR CoatingBrief Process Flow - Contact Plug Contact Mask PR coatingContact

36、PRMetal 111. Contact Plug Formation :11.1 Contact Lithography11.2 Contact Plasma Etching11.3 PR strip11.4 Barrier layer deposition(Ti + TiN for well contact)11.5 RTP annealing11.6 Glue Layer deposition(Ti + TiN for plug adhesion)11.5 WCVD filling11.6 WCMP11.7 Metal Liner deposition(Ti + TiN for Meta

37、l adhesion)11.8 Metal SputterBrief Process Flow - Backend routine (Aluminum line)P-subNWELLSTIPWELLPolyPR coatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN+ PRN+N+P+ PRP+SABPSGUSGPR Coating Contact Mask PR coatingContact PRMetal 1Contact plugPR CoatingMetal 1 maskMetal 1 PRMetal 1HDP-1PE

38、OXCap Oxide PR CoatingMVIA1 maskMVIA1 PRMetal 2 12. IMD deposition12.1 HDP-Oxide deposition( Gap filling)12.2 PE-Oxide Deposition( Planarization and uniformity)12.3 IMD CMP12.4 Cap PE-Oxide13. MVIA plug formation13.1 MVIA Lithography cycle13.2 MVIA Etching and PR strip13.3 Glue Layer deposition(Ti +

39、 TiN for plug adhesion)13.4 WCVD filling13.5 WCMP13.6 Metal Liner deposition(Ti + TiN for Metal adhesion)13.7 Metal SputterBrief Process Flow - Aluminum lineMVIA1MVIA2MVIA3MVIA4MVIA5PassivationM5-8KM6-8KM4-5KM3-5KM2-5KM1-5KUMC.Fab8B. Generic 0.25um logic Ti-Salicide ProcessP-subNWELLSTIPWELLPolyPR c

40、oatingPoly Mask NLDDN-LDDN-PKTN-LDDN-PKTP-LDD PR P-LDDP-PKTN+ PRN+N+P+ PRP+SABPSGUSGContact plugBrief Process Flow - Backend routine(Copper Dual Damascene)PR CoatingMetal 1 maskMetal 1Metal 2 MaskMVIA1 MaskMetal 214. ILD/M1 Damascene14.1 PEOX-3.6K deposition14.2 M1 Lithography14.3 M1 Trench Etching1

41、4.4 M1 Cu Electroplate (ECP)14.5 Cu CMP15. M2/ MVIA1 Dual Damascene15.1 PEOX-9K deposition15.2 M2 Lithography15.3 M2 Trench Etching15.4 MVIA1 Lithography15.5 MVIA1 Plug Etching15.6 Trench Liner deposition15.7 M2/MVIA1 Cu ECP15.8 Cu CMPHierarchy of IC ChipMultilevel MetallizationM1ContactVia 1M2Via 2

42、M3Via 3M4IMD3ILDIMD1IMD2Backend processFrontendActiveAreaDiffusion Barrier/Adhesion PromoterPlug电晶体电晶体 (晶体管晶体管) MOSFET: Metal-Oxide-Semiconductor Field-Effect Transistor连接线连接线Thank you 谢谢谢谢Q&A 请您提问请您提问Si3N4 (氮化硅氮化硅)Example (案例探讨案例探讨) How ?(如何做如何做 ?)(a)WET (酸槽酸槽)(清洗清洗)(b) Diffusion or Thin-Filmnitride (氮化硅氮化硅)(薄膜薄膜沉积沉积)(c) CMP (化学机械研磨化学机械研磨)硏磨硏磨平坦化平坦化(d) PHOTO (黃光黃光)Mask (光罩光罩)特殊特殊光线光线曝光曝光区区光光 阻阻光光 阻阻(e) ETCH (蚀刻蚀刻)光光 阻阻光光 阻阻Etching gas(蚀刻气体蚀刻气体)(f) ETCH (蚀刻后蚀刻后)光光 阻阻光光 阻阻WET (酸槽酸槽)(g) WET (光阻去除光阻去除后后)結果結果