《EDA考试题目和答案(共41页).doc》由会员分享，可在线阅读，更多相关《EDA考试题目和答案(共41页).doc（41页珍藏版）》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。
1、精选优质文档-倾情为你奉上设计实验与考核1、 设计一个带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter is port(clk,clk1,en,clr:in std_logic; ledout:out std_logic_vector(6 downto 0); scanout,scanout1,co:out std_logic);end counter;architecture
2、a of counter issignal cnt:std_logic_vector(7 downto 0);signal led:std_logic_vector(6 downto 0);signal scan:std_logic;signal hex:std_logic_vector(3 downto 0);begin process(clk) begin if(clkevent and clk=1)then if en=1then if clr=1then cnt0); else if cnt=then cnt=; co=1; else cnt=cnt+1; co=0; end if;
3、end if; end if; end if; end process;process(clk1) begin if clk1event and clk1=1then scan=not scan; end if;Scanout=scan;Scanout1=not scan;end process;ledout=not led;hex=cnt(7 downto 4) when scan=1else cnt(3 downto 0);with hex selectled=when0001, when0010, when0011, when0100, when0101, when0110, when0
4、111, when1000, when1001, when1010, when1011, when1100, when1101, when1110, when1111, when others;end a;2、 设计一个带计数使能、同步复位、带进位输出的增1二十进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter isport(clk,clk1,en,clr:in std_logic; co,scanout:out std_l
5、ogic; ledout:out std_logic_vector(6 downto 0);end counter;architecture rtl of counter is signal cnt:std_logic_vector(7 downto 0); signal led:std_logic_vector(6 downto 0); signal scan:std_logic; signal hex:std_logic_vector(3 downto 0);begin process(clk,clr) begin if clr=1then cnt0); elsif clkevent an
6、d clk=1 then if en=1then if cnt=then cnt=; co=0; elsif cnt=then -注意此处，前面跳过了A到F的计数,所以计数到11001 cnt=; co=1; else cnt=cnt+1; co=0; end if; end if; end if; end process; process(clk1) begin if clk1event and clk1=1then scan=not scan; end if; end process; ledout=not led; scanout=scan; hex=cnt(7 downto 4) wh
7、en scan=1else cnt(3 downto 0); with hex select led=when0001, when0010, when0011, when0100, when0101, when0110, when0111, when1000, when1001, when0000, when others;end rtl;3、 设计一个带计数使能、异步复位、同步装载的可逆七位二进制计数器，计数结果由共阴极七段数码管显示。答：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;enti
8、ty counter isport(clk,clks,clr,en,stdl,dir:in std_logic; din:in std_logic_vector(6 downto 0); ledout:out std_logic_vector(6 downto 0); scanout:out std_logic);end counter;architecture a of counter is signal cnt:std_logic_vector(6 downto 0); signal hex:std_logic_vector(3 downto 0); signal led:std_logi
9、c_vector(6 downto 0); signal scan:std_logic;begin process(clk) begin if(clkevent and clk=1)then if clr=1then cnt0); elsif stdl=0then cnt=din; elsif en=1then if dir=1then cnt=cnt+1; else cnt=cnt-1; end if; end if; end if; end process; process(clks) begin if(clksevent and clks=1)then scan=not scan; en
10、d if; end process; scanout=scan; ledout=not led; hex=0&cnt(6 downto 4)when scan=1 else cnt(3 downto 0); with hex select led=when0001, when0010, when0011, when0100, when0101, when0110, when0111, when1000, when1001, when1010, when1011, when1100, when1101, when1110, when1111, when others;end a;4、 设计一个带
11、计数使能、同步复位、异步装载、可逆计数的通用计数器。计数结果由共阴极七段数码管显示。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY counter IS GENERIC (count_value:INTEGER:=9);PORT(clk,clr,en,load,dir:IN STD_LOGIC; data_in:IN INTEGER RANGE 0 TO count_value; ledout:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);END counte
12、r;ARCHITECTURE a OF counter IS SIGNAL cnt:INTEGER RANGE 0 TO count_value; SIGNAL led:STD_LOGIC_VECTOR(6 DOWNTO 0);BEGIN PROCESS(load,clk) BEGIN IF load=1 THEN cnt=data_in; elsif clr=1 THEN cnt=0; ELSIF (clkEVENT AND clk=1)THEN IF en=1 THEN IF dir=1 THEN IF cnt=count_value THEN cnt=0; ELSE cnt=cnt+1;
13、 end if; else IF cnt=0 THEN cnt=count_value; else cnt=cnt-1; end if; end if; end if; end if; END PROCESS; ledout=NOT led; WITH cnt SELECT led=WHEN 1, WHEN 2, WHEN 3, WHEN 4, WHEN 5, WHEN 6, WHEN 7, WHEN 8, WHEN 9, WHEN 0, WHEN others;END a;5、 设计一个具有16分频、8分频、4分频和2分频功能的多用分频器。答：LIBRARY IEEE;USE IEEE.ST
14、D_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY div4 ISPORT(clk:IN STD_LOGIC; din:IN STD_LOGIC_VECTOR(3 DOWNTO 0); fout:OUT std_LOGIC);END div4;ARCHITECTURE a OF div4 ISbegin process(clk) variable cnt:std_logic_vector(3 downto 0); begin if(clkevent and clk=1) then if cnt=1111 then cnt:=0000;
15、 else cnt:=cnt+1; end if; if din=0000 then fout=cnt(3); elsif din=1000 then fout=cnt(2); elsif din=1100 then fout=cnt(1); elsif din=1110 then fout=cnt(0); else fout=1; end if; end if; end process;end a;6、 设计一个正负脉宽相等的通用分频器。答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENT
16、ITY div ISGENERIC (num:INTEGER:=2);PORT (clk:IN STD_LOGIC; co:OUT STD_LOGIC);END div;ARCHITECTURE rtl OF div ISBEGIN PROCESS(clk) VARIABLE cnt:STD_LOGIC_VECTOR(num downto 0); BEGIN IF(clkevent and clk=1)THEN cnt:=cnt+1; END IF; co=0101)then cnt:=0000; else cnt:=cnt+1; end if; cout=1000)then cnt:=000
17、0; cout=1; else cnt:=cnt+1; cout=1110)then cnt:=0000;cout=1; else cnt:=cnt+1;cout=1111)then cnt:=0000; else cnt:=cnt+1; end if; cout=cnt(3); end if;end if;end process; with en select led=when00, when01, when10, when11, when others;ledout=led;end dgnfenpin;8、 设计一个M序列发生器，M序列为“”library ieee;use ieee.st
18、d_logic_1164.all;use ieee.std_logic_unsigned.all;entity xulie isport(clk:in std_logic; fout:out std_logic);end xulie;architecture fashengqi of xulie issignal cnt:std_logic_vector(2 downto 0);beginprocess(clk)beginif(clkevent AND clk=1)then if(cnt=111)then cnt=000; else cnt=cnt+1; end if;end if;end p
19、rocess;with cnt select fout=1when000, 1when001, 1when010, 1when011, 0when100, 1when101, 0when “110”,1when”111”, 0when others;end fashengqi;9、 设计一个彩灯控制器，彩灯共有16个，每次顺序点亮相邻的四个彩灯，如此循环执行，循环的方向可以控制。答：library ieee;use ieee.std_logic_1164.all;entity caideng isport( rl,clk:in std_logic;ledout:out std_logic_ve
20、ctor(15 downto 0);end caideng;architecture a of caideng issignal led:std_logic_vector(15 downto 0);signal k:std_logic;beginprocess(clk)beginif(clkevent and clk=1)then if(k=0)then led1,1=1,2=1,3=1,others=0); elsif(rl=1)then led=led(14 downto 0)&led(15); elsif(rl=0)then led=led(0)&led(15 downto 1); en
21、d if;end if;ledout=led;end process;end a;10、 设计一个具有左移、右移控制，同步并行装载和串行装载的8位串行移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY shifter1 ISPORT(clk,clr,ser,dir,stld:IN STD_LOGIC;din: IN STD_LOGIC_VECTOR(0 TO 7) ;qh:OUT STD_LOGIC);END shifter1;ARCHITECTURE rt1 OF shifter1 ISSIGNAL reg:STD_LOGIC_VECTO
22、R(0 TO 7);beginprocess(clk,clr)beginif clr=1 thenreg0);elsif clkevent and clk=1then if stld=0then reg=din; else if(dir=0)then reg=reg(1 to 7)&ser;qh=reg(0); else reg=ser®(0 to 6);qh=”0101”and cnt=”1001”)then gree=1;red=”0000”and cnt=”0100”)thengree=0;red=1; end if;count=cnt;end process;ledout=not
23、 led;with count selectled=when0001,when0010,when0011,when0100,when0101,when0110,“”when”0111”,“”when”1000”,“”when”1001”,when others;end rtl;12、 设计一个同步复位，异步并行装载的8位串行左移移位寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;Entity exam13 isPort(clk,clr,ser,stld:in std_logic;Din:in std_logic_vector(0 to 7);Qh:out
24、 std_logic);End exam13;Architecture rtl of exam13 isSignal reg:std_logic_vector(0 to 7);BeginProcess(clk,stld)Begin If stld=1 thenReg=din; Elsif clkevent and clk=1 thenIf clr=1 then Reg=0);Elsif(stld=0)then Reg=reg(1 to 7)&ser;End if; End if;End process;Qh=reg(0);End rtl;13、 有16个开关，编号为0到15，编号0的优先级最高
25、。当某一个拨码开关为1时由共阴极七段数码管显示其编号（可用16进制数显示，亦可用十进制显示）答：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY bhxs ISPORT(INPUT:IN STD_LOGIC_VECTOR(15 DOWNTO 0); LEDOUT: out STD_LOGIC_VECTOR(6 DOWNTO 0);END bhxs;ARCHITECTURE RT1 OF bhxs IS SIGNAL LED:STD_LOGIC_VECTOR(6 DOWNTO 0);BE
26、GIN process(INPUT) begin LEDOUT=NOT LED; IF(INPUT(0)=1)then LED=; ELSIF(INPUT(1)=1)then LED=; ELSIF(INPUT(2)=1)then LED=; ELSIF(INPUT(3)=1)then LED=; ELSIF(INPUT(4)=1)then LED=; ELSIF(INPUT(5)=1)then LED=; ELSIF(INPUT(6)=1)then LED=; ELSIF(INPUT(7)=1)then LED=; ELSIF(INPUT(8)=1)then LED=; ELSIF(INPU
27、T(9)=1)then LED=; ELSIF(INPUT(10)=1)then LED=; ELSIF(INPUT(11)=1)then LED=; ELSIF(INPUT(12)=1)then LED=; ELSIF(INPUT(13)=1)then LED=; ELSIF(INPUT(14)=1)then LED=; ELSIF(INPUT(15)=1)then LEDjiashui=0;qidong=1; If water_low=1then next_state=too_low; Elsif water_high=1then next_state=too_high; Else nex
28、t_statejiashui=1;qidong=0; If water_low=1then next_state=too_low; Elsif water_high=1then next_state=too_high; Else next_statejiashui=0;qidong=1; If water_low=1then next_state=too_low; Elsif water_high=1then next_state=too_high; Else next_state=just_right; End if; End case, End process;Process(clk) B
29、egin If(clkevent and clk=1)then Now_state=next_state; End if; End process;End style;15、 根据真值表设计一位全加器，然后用结构的描述方法设计一个8位加法器。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY full_adder ISPORT(a,b,cin:IN STD_LOGIC; s,co:OUT STD_LOGIC);END full_adder;ARCHITECTURE full1 of full_adder isSIGNAL comb:STD_LOGIC
30、_VECTOR(2 downto 0);BEGIN comb=a&b&cin;PROCESS(comb)BEGINIF(comb=000)then s=0;co=0;elsif(comb=001)then s=1;co=0;elsif(comb=100)then s=1;co=0;elsif(comb=010)then s=1;co=0;elsif(comb=011)thens=0;co=1;elsif(comb=101)thens=0;co=1;elsif(comb=110)thens=0;co=1;elses=1;co=1;end if;end process;end full1;libr
31、ary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity full_adder8 isport(clk,cin:in std_logic; x,y:in std_logic_vector(7 downto 0); ledout:out std_logic_vector(6 downto 0);scan_out:out std_logic_vector(1 downto o); co:out std_logic);end full_adder8;
32、architecture stru of full_adder8 iscomponent full_adderport(a,b,cin:in std_logic; s,co:out std_logic);end component; signal z:std_logic_vector(6 downto 0);signal sum:std_logic_vector(7 downto 0);signal scan:std_logic_vector(1 downto 0);signal hex:std_logic_vector(3 downto 0);signal led:std_logic_vec
33、tor(6 downto 0);beginuo:full_adder port map(x(0),y(0),cin,sum(0),z(0);u1:full_adder port map(x(1),y(1),z(0),sum(1),z(1);u2:full_adder port map(x(2),y(2),z(1),sum(2),z(2);u3:full_adder port map(x(3),y(3),z(2),sum(3),z(3);u4:full_adder port map(x(4),y(4),z(3),sum(4),z(4);u5:full_adder port map(x(5),y(5),z(4),sum(5),z(5);u6:full_adder port map(x(6),y(6),z(5),sum(6),z(6);u7:full_adder port map(x(7),y(7),z(6),sum(7),co);scan_out=scan;ledout=not led;process(clk)b