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1、精选优质文档-倾情为你奉上目录专心-专注-专业1.秒表设计要求（1） 秒表的计时范围为00：00：00 59：59：99。（2） 两个按钮开关Start/Stop和Split/Reset，控制秒表的启动、停止、分段和复位：在秒表已经被复位的情况下，按下“Start/Stop”键，秒表开始计时。在秒表正常运行的情况下，如果按下“Start/Stop”键，则秒表暂停计时；再次按下该键，秒表继续计时。在秒表正常运行的情况下，如果按下“Split/Reset”键，显示停止在按键时的时间，但秒表仍然在计时；再次按下该键，秒表恢复正常显示。在秒表暂停计时的情况下，按下“Split/Reset”键，秒表复位
2、归零。2.设计思路2.1功能模块2.1.1分频器对晶体振荡器产生的时钟信号进行分频，产生时间基准信号2.1.2计数器对时间基准脉冲进行计数，完成计时功能2.1.3数据锁存器锁存数据使显示保持暂停2.1.4控制器通过产生锁存器的使能信号来控制计数器的运行、停止以及复位设计分析：2.1.5扫描显示的控制电路 包括扫描计数器、数据选择器和7段译码器，控制8个数码管以扫描方式显 示计时结果，原理图如下：实验电路板上的按键2.1.6显示电路2.1.7按键消抖电路消除按键输入信号抖动的影响，输出单脉冲实验板上的数码管为共阳LED数码管按键按下时，FPGA的输入为低电平；松开按键时，FPGA的输入为高电平但
3、是在按下按键和松开按键的瞬间会出现抖动现象2.2电路框图3.电路实现- Company: - Engineer: - - Create Date: 09:08:39 03/12/2011 - Design Name: - Module Name: stopwatch_1 - Behavioral - Project Name: - Target Devices: - Tool versions: - Description: - Dependencies: - Revision: - Revision 0.01 - File Created- Additional Comments: -lib
4、rary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity stopwatch_1 isPort (Clk : in STD_LOGIC;start_stop :
5、 in STD_LOGIC;split_reset : in STD_LOGIC;ncs : out STD_LOGIC;s : out STD_LOGIC_VECTOR(2 downto 0);seg : out STD_LOGIC_VECTOR (7 downto 0);end stopwatch_1;architecture Behavioral of stopwatch_1 issignal k1,k2,k3,k4: STD_LOGIC;signal cnt_1,cnt_2 : STD_LOGIC_VECTOR(1 downto 0);signal start_stop_out,spl
6、it_reset_out: STD_LOGIC;signal count: STD_LOGIC_VECTOR(15 downto 0):=(others=0);signal clk_1k: STD_LOGIC;signal z0,z1,z2,z3,z4,z5,z6,q1,q2,q3,q4,q5,q6 : STD_LOGIC_VECTOR(3 downto 0):=(others=0);signal count_2: STD_LOGIC_VECTOR(2 downto 0 ):=(others=0);signal in_7: STD_LOGIC_VECTOR(3 downto 0);signal
7、 sreg: STD_LOGIC_VECTOR(2 downto 0):=111;signal snext: STD_LOGIC_VECTOR(2 downto 0);Begin-为三八译码器置入使能信号 ncs = 0;-分频电路process(clk)beginif rising_edge(clk) thenif count = 47999 thencount 0);elsecount = count+1;end if;end if;end process;clk_1k = count(15);-同步计数电路process(clk_1k,sreg(2)beginif rising_edge
8、(clk_1k) thenif sreg(2) = 1 then z00);z10);z20);z30);z40);z50);z60);elsif sreg(1) = 1 thenz0 = z0+1;if z0 = 9 thenz0 0);z1 = z1+1;if z1 = 9 thenz1 0);z2 = z2+1;if z2 = 9 thenz2 0);z3 = z3+1;if z3 = 9 thenz3 0);z4 = z4+1;if z4 = 5 thenz4 0);z5 = z5+1;if z5 = 9 thenz5 0);z6 = z6+1;if z6 = 5 thenz6 0);
9、end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;-扫描计数器process(clk_1k)beginif rising_edge(clk_1k) thencount_2 = count_2+1;end if;end process;s = count_2;-锁存器process(sreg(0),z1,z2,z3,z4,z5,z6)beginif sreg(0) = 1 thenq1 = z1;q2 = z2;q3 = z3;q4 = z4;q5 = z5;q6 in_7 in_7 in_7 i
10、n_7 in_7 in_7 in_7 seg seg seg seg seg seg seg seg seg seg seg =;end case;end process;-按键去抖电路process(clk_1k,start_stop)beginif clk_1kevent and clk_1k=0 thenifcnt_1 = 3 thenk1 = 1;elsek1 = 0;cnt_1 = cnt_1+1;end if;k2 = k1;end if;if start_stop = 0 thencnt_1 = 00;end if;end process;start_stop_out = not
11、 k1 and k2; process(clk_1k,split_reset)beginif clk_1kevent and clk_1k=0 thenifcnt_2 = 3 thenk3 = 1;elsek3 = 0;cnt_2 = cnt_2+1;end if;k4 = k3;end if;if split_reset = 0 thencnt_2 = 00;end if;end process;split_reset_out = not k3 and k4;-控制器 process(clk_1k,start_stop_out,split_reset_out)beginif rising_e
12、dge(clk_1k) thensreg if start_stop_out = 1 and split_reset_out = 0 then snext = 011;else snext if start_stop_out = 1 and split_reset_out = 0 then snext = 001;elsif start_stop_out = 0 and split_reset_out = 1 then snext = 010;else snext if start_stop_out = 0 and split_reset_out = 1 then snext = 111;el
13、sif start_stop_out = 1 and split_reset_out = 0 then snext = 011;else snext if start_stop_out = 0 and split_reset_out = 1 then snext = 011;else snext snext 0);beginprocess(clk_48M)beginif rising_edge(clk_48M) thenif count = 47999 thencount 0);elsecount = count+1;end if;end if;end process;clk_1k = cou
14、nt(15);end Behavioral;tb : PROCESSBEGINclk_48M = 1; wait for 10.4 ns;clk_48M 0);signal clr,en: STD_LOGIC;Beginclr = 0; -清零无效en = 1; -计数使能有效d1 = z1;d2 = z2;d3 = z3;d4 = z4;d5 = z5;d6 = z6;process(clk_1k,clr)beginif rising_edge(clk_1k) thenif clr = 1 then z00);z10);z20);z30);z40);z50);z60);elsif en =
15、1 thenz0 = z0+1;if z0 = 9 thenz0 0);z1 = z1+1;if z1 = 9 thenz1 0);z2 = z2+1;if z2 = 9 thenz2 0);z3 = z3+1;if z3 = 9 thenz3 0);z4 = z4+1;if z4 = 5 thenz4 0);z5 = z5+1;if z5 = 9 thenz5 0);z6 = z6+1;if z6 = 5 thenz6 0);end if;end if;end if;end if;end if;end if;end if;end if;end if;end process;end Behav
16、ioral;4.2.2计数器仿真tb : PROCESSBEGINclk_1k = 0;wait for 0.5 ms;clk_1k = 1;wait for 0.5 ms;END PROCESS;0.01s位由图可以看出为十进制0.1s位由图可以看出为十进制1s位由图可以看出为十进制10s位由图可以看出为六进制1min位由图可以看出为十进制10min位由图可以看出为六进制4.2.3同步计数器电路综合 4.3按键消抖电路4.3.1按键消抖电路实现entity quedou is Port ( clk_1k : in STD_LOGIC; key_in : in STD_LOGIC; key_o
17、ut : out STD_LOGIC);end quedou;architecture Behavioral of quedou issignal k1,k2: STD_LOGIC;signal cnt_1: STD_LOGIC_VECTOR(1 downto 0);beginprocess(clk_1k,key_in)beginif clk_1kevent and clk_1k=0 thenifcnt_1 = 3 thenk1 = 1;elsek1 = 0;cnt_1 = cnt_1+1;end if;k2 = k1;end if;if key_in = 0 thencnt_1 = 00;e
18、nd if;end process;key_out = not k1 and k2;end Behavioral;4.3.2按键消抖电路仿真tb : PROCESSBEGINclk_1k = 0 ; wait for 0.5 ms;clk_1k = 1 ; wait for 0.5 ms;END PROCESS;PROCESSBEGINkey_in = 1;wait for 10 ms;key_in = 0;wait for 0.1 ms;key_in = 1;wait for 0.09 ms;key_in = 0;wait for 0.1 ms;key_in = 1;wait for 0.1
19、1 ms;key_in = 0;wait for 0.12 ms;key_in = 1;wait for 0.11 ms;key_in = 0;wait for 0.12 ms;key_in = 1;wait for 0.1 ms;key_in = 0;wait for 0.11 ms;key_in = 1;wait for 0.12 ms;key_in = 0;wait for 0.1 ms;key_in = 1;wait for 0.1 ms;key_in = 0;wait for 10 ms;key_in = 1;wait for 0.09 ms;key_in = 0;wait for
20、0.08 ms;key_in = 1;wait for 0.1 ms;key_in = 0;wait for 0.11 ms;key_in = 1;wait for 0.09 ms;key_in = 0;wait for 0.1 ms;key_in = 1;wait for 0.11 ms;key_in = 0;wait for 0.12 ms;key_in = 1;wait for 0.1 ms;key_in = 0;wait for 0.11 ms;key_in = 1;wait for 0.12 ms;key_in = 0;wait for 0.1 ms;key_in seg seg s
21、eg seg seg seg seg seg seg seg seg =;end case;end process;end Behavioral;4.4.2八段译码器仿真tb : PROCESSBEGINin_7 = 0000; wait for 1 ms;in_7 = 0001; wait for 1 ms;in_7 = 0010; wait for 1 ms;in_7 = 0011; wait for 1 ms;in_7 = 0100; wait for 1 ms;in_7 = 0101; wait for 1 ms;in_7 = 0110; wait for 1 ms;in_7 = 01
22、11; wait for 1 ms;in_7 = 1000; wait for 1 ms;in_7 = 1001; wait for 1 ms;in_7 = 1010; wait for 1 ms;in_7 = 0000; wait for 1 ms;END PROCESS;由图可见仿真结果与程序完全符合4.4.3八段译码器电路综合View Technology Schematic ：4.5控制器4.5.1控制器entity kongzhiqi is Port ( clk_1k : in STD_LOGIC; start_stop_out : in STD_LOGIC; split_reset
23、_out : in STD_LOGIC; sreg_out : out STD_LOGIC_VECTOR (2 downto 0);end kongzhiqi;architecture Behavioral of kongzhiqi issignal sreg: STD_LOGIC_VECTOR(2 downto 0):=111;signal snext: STD_LOGIC_VECTOR(2 downto 0);beginprocess(clk_1k,start_stop_out,split_reset_out)beginif rising_edge(clk_1k) thensreg if
24、start_stop_out = 1 and split_reset_out = 0 then snext = 011;else snext if start_stop_out = 1 and split_reset_out = 0 then snext = 001;elsif start_stop_out = 0 and split_reset_out = 1 then snext = 010;else snext if start_stop_out = 0 and split_reset_out = 1 then snext = 111;elsif start_stop_out = 1 a
25、nd split_reset_out = 0 then snext = 011;else snext if start_stop_out = 0 and split_reset_out = 1 then snext = 011;else snext snext = 111;end case;end process;sreg_out = sreg ;end Behavioral;4.5.1控制器仿真tb : PROCESSBEGINclk_1k = 0;wait for 0.5 ms;clk_1k = 1;wait for 0.5 ms;END PROCESS;PROCESSBEGINstart
26、_stop_out = 1 ;wait for 1 ms;start_stop_out = 1 ;wait for 1 ms;start_stop_out = 1 ;wait for 1 ms;start_stop_out = 0 ;wait for 1 ms;start_stop_out = 0 ;wait for 1 ms;start_stop_out = 1 ;wait for 1 ms;start_stop_out = 0 ;wait for 1 ms;END PROCESS;PROCESSBEGINsplit_reset_out = 0;wait for 1 ms;split_reset_out = 0;wait for 1 ms;split_reset_out = 0;wait for 1 ms;split_reset_out = 1;wait for