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1、精选优质文档-倾情为你奉上Design and Implementation ofDigital Cymometer Based on CPLDAbstractWith the adoption of the top-down design method and AT89C51 SCMC (Single Chip Mico Computer) as the master control component of the system ,the circuit test signalcontrolling ,data operation processing ,keyboard scanning
2、 ,and nixie tube display as well were completed by the digital cymometer.A CPLD ,EPM7128SLC84-15 ,programmed by VHDL ,realized various sequence control and count functions .The system is characterized by impact structure ,high reliability ,high precision ,and wide frequency-test-range .Keywords digi
3、tal cymometer，complex programmable logic device，SCMC，EDA technology1 IntroductionThe system core called SCMC (Single Chip Mico Computer) emerges constantly despite the unceasing development of electronic and computer technologies.The frequency measurement or cycle measurement is usually utilized for
4、 testing signals that use frequency as a parameter. When the tested frequency is relatively high ,relatively high precision can be available with frequency measurement . When the tested frequency isrelatively low ,relatively high precision can be a vailable with cycle measurement . However , neither
5、 of them can ensure the measurement precision in the whole frequency range ,when the range of tested frequency is comparatively wide .This digital Cymometer utilizes the advanced EDA technology and top-down design method . Thus ,the Cynometer implements the equal precision measurement of the signal
6、frequency range of 0.1 Hz50MHzby AT89C51 SCMC and CPLD，and also measures pulse width and duty ratio . Because of the convenience of CPLD programming ,quick speed , high integration , and low price , the system research circle is extremelyshortened and the product ratio of performance versus price is
7、 improved . The CPLD chip employs the popular VHDL and achieves all the program design and Download on the MAX+PlusII software platform . The control portion of SCMC ,programmed by assemble language precisely sets time , exactly controls startup and closedown of frequency-test count strobe ,which fu
8、rther ensures measurement precision . System theory and software & hardware design are introduced below .2 Equal precision measurement theoryIn CPLD ,top-level circuit structure realized by VHDL is shown in figure 1 ,where CONTROL1 is control module of frequency-est ,CONTROL2 is control module of pu
9、lse-width-test and duty ratio,CHOICE is choice module of self-djustment and measurement ;COUNT is count module of datum frequency and frequency-test . Under the control of SCMC ,the CPLD accomplishes frequency-test in the following steps :(a) Plus pulse signal is added at CLR , thereby completing th
10、e initialization of testing circuit state (when frequency is tested ,CS ,AS is low ,ED2 is irrelevant ) .(b) When strobe signal STROBE is set high ,timing starts . Meanwhile ,rising edge of pulse-test signal Fx ,which is selected by CHOICE module , initiates frequency-test control module CONTROL1 ,
11、which makes two sets of 32-bit counter within COUNT take count of datum frequency signal Fs and signal-test Fx synchro no usly .(c) STROBE is set low when stro be timing ends . COUNT stops counting once rising edge of next pulse of signal-test advents .(d) After count finishes ,ED1 outputs low level
12、 to apply for interrupt from SCMC. In the Interrupt Service Routine ,SCMC reads count value of datum frequency signal and signal-test in COUNT from port P0 and P2 of SCMC for four times , through encoding address line SS1 and SS0 . If the count value of signal-test is Nx ,datum frequencys is Ns ,the
13、n Fx=( Fs/ N s) N x . Fig . 1 Frequency measurement top-level module3 Design of system hardware circuitThe block diagram of system hardware circuit is shown in f igure 2 .There is a 4 kB Flash Memory in A T89C51 SCMC into which all control program can be stored . SCMC writes the result tested from C
14、PLD each time into RAM ,and t hen sends it in decimal into eight-bit nixie tube display circuit to display after operation processing . Keyboard control command is written into SCMC via a 74LS165 ,Parallel in/ Serial Output Shift Registers . SCMC utilizes one 12MHz crystal whose oscilla-tion pulse i
15、s served as self-adjustment input of CPLD at the same time . Signal-test is inputted to CPLD via wide band amplify and Schmitt circuit shape . 50MHz active crystal module is used for datum frequency input .4 VHDL program designCPLD software program is achieved by VHDL . A portion of top-level module
16、 program is as follow :LIBRARY IEEE ;USE IEEE. STD_LOGIC_1164 . ALL ;USE IEEE. STD_LOGIC_UNSIGNED . ALL ;ENTITY FREQUENCY8 ISPORT ( SS0 ,SS1 ,FS ,FX ,FC ,CLR ,AS ,STROBE ,CS : IN STD_LOGIC ;ED1 , ED2 :OUT STD_LOGIC ;B :OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ;END FREQUENCY8 ;ARCHITECTURE RTL OF FREQUEN
17、CY8 ISSIGNAL FX0 ,CLKX ,CLKS ,CLE ,SSL1 : STD_LOGIC ;COMPONENT COUNTPORT ( FX1 ,FS1 ,CLR ,SS0 ,SS1 : IN STD_LOGIC ;B :OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ;END COMPONENT ;BEGINU1 :CHOICE PORT MAP ( FX = FX ,FC = FC ,AS =AS ,FOUT =FX0) ;U2 :CONTROL1 PORT MAP( FX1=FX0 , STROBE =STROBE ,CLR=CLR , FS=FS
18、 ,CS =CS ,SSL=SSL1 ,CLK1=CLKX ,CLK2 =CLKS ,CLRC =CLE ,ED1 = ED1) ;U3 :CONTROL2 PORT MAP( FIN=FX0 ,STROBE = STROBE ,CLR=CLR ,SSL=SSL 1 ,ED2=ED2) ;U4 :COUNT PORT MAP(FX1=CLKX ,FS1=CLKS ,CLR=CLE ,SS0 = SS0 ,SS1 = SS1 ,B = B) ;END RTL ;Figure 3 is the emulation waveform diagram when signal-test Fx=10MHz
19、 and Fs=50MHz .Fig . 2 Emulation waveform diagram5 Frequency-test precision analysisFrom the frequency-test formula : Fx = (Fs/ Ns) Nx . Suppose that frequency-test is Fx ,its true value is Fxe ,and standard frequency is Fs. In one measurement ,because Fx count startup and closedown time are both tr
20、iggered by the signals rising edge ,count Nx of Fx has no error in one strobe time T ,while count Ns has error of one pulse at most , that is | et | 1 , we can derived Fxe =( Fs/(N s +et) ) Nx fromFx/Nx = Fs/Ns and Fxe/Nx = Fs/(Ns +et ) . According to relative error formula Fxe/ Fxe =| Fxe -Fx | /Fx
21、e ,we have Fxe/ Fxe = |et| /Ns. Then , since | et | 1 , we obtain | et | / N s 1/ Ns ,Ns = TFs.Accordingly we reach the conclusion that relative measurement error has no relation to frequency-test ,measurement error which can be reduced and measurement precision improved via augmenting strobe time T
22、 or enhancing Fs. The measurement precision of frequency-test system remains constant in the entire frequency range in case that strobe time and general frequency measurement strobe time is uniform and signal-test frequency is dissimilar .The range of this system frequency-test is set as from 0.1Hz
23、to 50MHz . Strobe time is set to two grades :1s and 10s . The strobe can test and obtain signal once every 10s when frequency-test is 0.1Hz .50MHz upper limit frequency setting depends on such factors as internal counter digit of CPLD , CPLD clock ,nixie tube digit ,and so on . In 10s strobe time ,5
24、0MHz datum frequency can count 500MHz pulse(only 29 bits binary number required) ,while 400MHz can be counted in theory as the 32-bit of signal-test is fully used in 10s . However ,because it is limited by two sets of global count clock ,which is 151.5MHz at most ,in EPM7128SLC84-15 chip selected by
25、 the system and the digit of 8-bit nixie tube , the upper limit frequency is restricted within 50MHz . In that case ,frequency-test whole-range relative error is millionth constantly .References :1 Song Pan , Guodong Wang . VHDL Application Course M . Chengdu :U niversity of Electronic Science and T
26、echnology Press ,2000 .2 Wanjie Song ,Ping Luo ,Shunjun Wu . CPLD Technology and Application M . Xian :Xian University of Electronic Science and Technology Press ,2000 .3 Bo heng Hou ,Xin Gu . VHDL Hardware Description Language and Digital Logic Circuit Design M . Xian : Xian University of Electroni
27、c Science and Technology Press ,2001 .基于复杂可编程逻辑器件的数字频率计的设计与实现摘要采用自上向下的设计方法,设计了基于复杂可编程逻辑器件的数字频率计。以AT89C51单片机作为系统的主控部件，完成电路的测试信号控制、数据运算处理、键盘扫描和控制数码管显示。用VHDL语言编程 ,由CPLD (Complex Programmable Logic Device) EPM7128SLC84-15 完成各种时序控制及计数功能。 该系统具有结构紧凑、可靠性高、测频范围宽和精度高等特点。关键词 数字频率计，逻辑器件，单片机，EDA 技术1引言随着电子技术与计算机技
28、术的不断发展，以单片机为核心的测量控制系统层出不穷。对于以频率为参数的被测信号，通常多采用的是测频法或测周法。当被测频率较高时，采用测频法可以得到较高的测频精度；当被测频率较低时，采用测周法可以得到较高的测频精度。但当被测频率变化范围较大时，这两种方法均不能保证整个频率范围的测量精度。该测频系统的设计扬弃了传统的自下而上的数字电路设计方法，采用先进的EDA技术及自上而下的设计，把资源丰富、控制灵活及良好人机对话功能的AT89C51单片机和具有内部结构重组、现场可编程的CPLD芯片完美的相结合起来，实现了对0.1Hz-50MHz信号频率的等精度测量。由于CPLD具有连续连接结构，易于预测延时，使
29、电路仿真会更加准确，且编程方便，速度快，集成度高，价格低，从而使系统研制周期大大缩短，产品的性能价格比捉高。CPLD芯片采用流行的VHDL语言编程，并在MAX+plus设计平台上实现了全部编程设计，单片机采用底层汇编语言编程，可以精确地控制测频计数闸门的开启和关闭，从而进一步提高了测量精度。该数字频率计的设计及实现具有良好的应用价值和推广前景。下面对系统的软硬件设计进行详细论述。2. 等精度测量原理CPLD利用VHDL语言实现的测频顶层电路模块逻辑结构如图1所示，其中CONTROL1为测频或测周期控制模块；CONTROL2为测脉宽和占空比控制模块；CHOICE为自校与测量选择模块；COUNT为
30、基准频率和被测频率计数器模块。在单片机的控制下，CPLD完成频率测量的步骤如下： (1)在CLR端加正脉冲信号完成侧试电路状态的初始化（当进行频率测量时，CS、AS为低电平，ED2 是不相干的）。 (2)由预置门控信号将STROBE置高电平，预置门开始定时，与此同时，被测脉冲信号FX经CHOICE选择后，启动频率测试控制模块CONTROL1, 被测信号的上升沿打开内含两套32位二进制计数器COUNT,同时对标准信号FS和被测信号FX进行计数。(3)顶置门定时结束信号把STROBE置为低电平，在被测信号的下一个脉冲的上沿到来时，COUNT停止计数。 (4)计数结束后，ED1端输出低电平来指示测量
31、计数结束，单片机得到此信号后，即可利用SSO, SS1 进行选择，四次分别读回COUNT中基准频率信号和被测信号计数值。设FX为整形后的被测信号，FS为标准频率信号，若在一次预置门高电平脉宽时间内被狈1信号计数值为Nx，基准频率计数值为Ns，则有: Fx=(Fs/Ns)Nx 图1 测频顶层模块逻辑电路3. 系统的硬件电路设计系统的硬件电路组成框图如图1-1所示。图中主控模块AT89C51是一个内含4K字节可编程可擦除的快闪存储器 (Flash Memory)的单片机。所有信号包括基准频率信号、被测信号以及自校输入信号均可在AT89C51单片机的控制下送入CPLD芯片中，单片机将每次测试结果读入
32、内存RAM中，经运算处理后，以十进制的形式送到8位数码管显示电路显示。键盘控制命令通过一片74LS165并入串出移位寄存器读入单片机。单片机由外接12MHz标准晶振提供时钟电路，同时输入CPLD的自校频率也取自单片机的外接晶振。用50MHz的有源晶振作为测试标准频率。4. VHDL程序设计CPLD的软件部分由VHDL语言实现，其顶层模块程序如下面所示：LIBRARY IEEE ;USE IEEE. STD_LOGIC_1164 . ALL ;USE IEEE. STD_LOGIC_UNSIGNED . ALL ;ENTITY FREQUENCY8 ISPORT ( SS0 ,SS1 ,FS ,
33、FX ,FC ,CLR ,AS ,STROBE ,CS : IN STD_LOGIC ;ED1 , ED2 :OUT STD_LOGIC ;B :OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ) ;END FREQUENCY8 ;ARCHITECTURE RTL OF FREQUENCY8 ISSIGNAL FX0 ,CLKX ,CLKS ,CLE ,SSL1 : STD_LOGIC ;COMPONENT COUNTPORT ( FX1 ,FS1 ,CLR ,SS0 ,SS1 : IN STD_LOGIC ;B :OUT STD_LOGIC_VECTOR (15 DOW
34、NTO 0) ) ;END COMPONENT ;BEGINU1 :CHOICE PORT MAP ( FX = FX ,FC = FC ,AS =AS ,FOUT =FX0) ;U2 :CONTROL1 PORT MAP( FX1=FX0 , STROBE =STROBE ,CLR=CLR , FS=FS ,CS =CS ,SSL=SSL1 ,CLK1=CLKX ,CLK2 =CLKS ,CLRC =CLE ,ED1 = ED1) ;U3 :CONTROL2 PORT MAP( FIN=FX0 ,STROBE = STROBE ,CLR=CLR ,SSL=SSL 1 ,ED2=ED2) ;U
35、4 :COUNT PORT MAP(FX1=CLKX ,FS1=CLKS ,CLR=CLE ,SS0 = SS0 ,SS1 = SS1 ,B = B) ;END RTL ;图2是当被测信号FX=10MHZ、FS=50MHZ时的仿真波形图。图2 仿真波形图5. 测频精度分析本系统的测频公式为：Fx=(Fs/Ns)Nx 。设所测频率值为Fx，其真实值为Fxe，标准频率为Fs。在一次测量中，由于Fx计数的起停时间都是由该信号的上跳沿触发的，在T时间内Fx的计数Nx无误差;此时内的计数Ns最多相差一个脉冲，即：|et|1则： Fx/Nx=Fs/Ns Fxe/Nx=Fs/ (Ns+et) 由此推得：Fx
36、=(Fs/Ns)*Nx Fxe=Fs/(Ns+et)*Nx根据相对误差公式有: Fxe/Fxe=|Fxe-Fe|/Fxe可以得：Fxe/Fxe=|et|/Ns |et|1 |et|/Ns1/Ns即|=Fxe/Fxe1/Ns Ns=T*Fs.因此，我们得出结论认为：相对测量误差与频率无关，通过增大预置门时间T和提高标准频率FS,可以增大标准频率计数值，减少测量误差，提高测量精度。在预置门时间和常规测频闸门时间相同而被测频率不同的情况下，本测频系统所采用的测量方法的测量精度不变。本系统的测频范围设置为0.1MHz50MHz. 预置门的时间值设定为两个等级：1秒和10秒。当采用10秒档时，被测频率为
37、0.1Hz时，可以检测到10秒闸门信号一次。50MHz上限频率设定受到CPLD内部 32位计数长度和CPLD本身计数时钟频率及8位数码管位数的限制。在 10秒的闸门时间内，50MHz的基准频率可以计500M计数脉冲(只需29位二进制有效数)，而被测信号在10秒内32位满量程，理论上可测试400M的频率。但由于系统选用的EPM7128SLC84-15芯片两套全局计数时钟最高为151. 1MHz及8位数码管的位长，故上限定界为50MHz。测频全域内相对误差恒为百万分之一。参考文献：1 潘松,王国栋编著. VHDL实用教程M. 成都:电子科技大学出版社，2000.2 宋万杰,罗平,吴顺君. CPLD技术及其应用M. 西安:西安电子科技大学出版社，2000.3 侯伯亨,顾新.VHDL硬件描述语言与数字逻辑电路设计M. 西安:西安电子科拄大学出版，2001.专心-专注-专业