《外文翻译--基于FPGA的数字频率计设计(共13页).doc》由会员分享，可在线阅读，更多相关《外文翻译--基于FPGA的数字频率计设计(共13页).doc（13页珍藏版）》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。
1、精选优质文档-倾情为你奉上武汉轻工大学毕业设计外文参考文献译文本2013届原文出处：from Vin Skahill.VHDL for Programmable Logic page 76-88毕业设计题目：基于FPGA的数字频率计设计院（系）：电气与电子工程学院 专业名称：电子信息科学与技术学生姓名： 学生学号： 指导教师： 专心-专注-专业 Introduction of digital frequency meterDigital Frequency is an indispensable instrument of communications equipment, audio and
2、 video, and other areas of scientific research and production . In addition to the plastic part of the measured signal, and digital key for a part of the show, all the digital frequency using Verilog HDL designed and implemented achieve in an FPGA chip. The entire system is very lean, flexible and h
3、ave a modification of the scene.1 、And other precision measuring frequency PrincipleFrequency measurement methods can be divided into two kinds: (1) direct measurement method, that is, at a certain time measurement gate measured pulse signal number. (2) indirect measurements, such as the cycle frequ
4、ency measurement, VF conversion law. Frequency Measurement indirect measurement method applies only to low-frequency signals.Based on the principles of traditional frequency measurement of the frequency of measurement accuracy will be measured with the decline in signal frequency decreases in the mo
5、re practical limitations, such as the accuracy and frequency of measurement not only has high accuracy, but also in the whole frequency region to maintain constant test accuracy. The main method of measurement frequency measurement Preferences gated signal GATE issued by the MCU, GATE time width on
6、the frequency measurement accuracy of less impact, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M Signals are not overflow line, in accordance with the theoretical calculation GATE time can be greater than the width Tc 42.94 s, but due to the single-chip microco
7、mputer data processing capacity constraints, the actual width of less time, generally in the range of between 0.1 s choice, that is, high-frequency, shorter gate;, low gate longer. This time gate width Tc based on the size of the measured frequency automatically adjust frequency measurement in order
8、 to achieve the automatic conversion range, and expanded the range of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.The design of the main methods of measuring the frequency measurement and control block diagram as shown in
9、 Figure 1. Figure 1 Preferences gated signal GA TE issued by the MCU, GA TE time width of less frequency measurement accuracy, in the larger context of choice, as long as the FPGA in 32 of 100 in the counter b M signal Overflow will do, according to theoretical calculations GA TE time width T c can
10、be greater than 42194 s, but due to the single-chip microcomputer data processing capacity constraints, the actual width of less time, generally 10 to 011 s in the inter-choice, that is, high - band, the gate time shorter, low gate longer. This time gate width based on the measured T c automatically
11、 adjust the size of frequency measurement frequency range to achieve the automatic conversion, and expanded the range of frequency measurement; realization of the entire scope of measurement accuracy, reduce the low-frequency measurement error.2、 Frequency of achievingFrequency Measurement accuracy
12、of such method. Can be simplified as shown in the diagram. Map CNT1 and CNT2 two controllable counter, standard frequency (f) signal from the CN F1 clock input cI K input, the signal measured after the plastic (f) CNT2 clock input cI K input. Each counter in the CEN input as enable end, used to cont
13、rol the counter count. When the gate signal is HIGH Preferences (Preferences start time). Signal measured by the rising edge of the D flip-flop input, launched at the same time with two counts of juice; Similarly, when preferences for low gate signal (the end of Preferences time), the rising edge of
14、 the measured signals through D Trigger output end of the counter to stop counting.3、And the median frequency of relevant indicatorsMedian: At the same time the figures show that up to the median. The usual eight-count frequency of only several hundred yuan can buy. For high precision measurements,
15、nine just beginning, the middle is 11, 13 can be relatively high. Overflow of:-the ability to promote itself to overflow the equivalent of the total. Some of the frequency with overflow function, which is the highest overflow does not display only shows that the bit behind, in order to achieve the p
16、urpose of the median. Here is the estimated value of individual indicators. Speed: namely, the number of per second. With the high number of measurement particularly slow but also lose its significance. Counting of the usual eight frequency measurement 10 MHz signals, one second gate will be Hz, whi
17、ch is actually seven (equivalent to the median number of common admission after the value), to obtain eight needed 10 seconds gate ; to obtain nine needed 100 seconds gate, followed by analogy, shows that even the permission of 11 need 10,000 second measurement time. But in any case, or seven per se
18、cond. Therefore, to fast must be a few high speed. Distinction: it is like a minimum voltage meter can tell how much voltage indicators are similar, the smaller the better, unit ps (picoseconds). 1000ps = 1ns. Suppose you use the frequency of 1 ns to differentiate between an e-12 error, we need a ns
19、/1e-12 = 1000 seconds. Also assume that you have a frequency resolution of 100 ps, the measurement time can be shortened by 10 times for 100 seconds, or can be in the same 1000 second measured under an e-14 Error.4、 Time and Frequency MeasurementCompared to traditional methods of circuit design, EDA
20、 technology uses VHDL language to describe circuit system, including circuit structure, behavior, function and interface logic. Verilog HDL description of a multi-level system hardware functions, and support top-down design features. Designers can not understand the hardware structure. Start from th
21、e system design, on the top floor of a system block diagram of the structure and design, in a diagram with Ver-ilog HDL acts on the circuit description and simulation and error correction, and then the system level verification, and finally use logic synthesis optimization tool to create specific ga
22、te-level logic circuit netlist, download to the specific FPGA device to in order to achieve FPGA design. Time and frequency measurement is an important area of electronic measurement. Frequency and time measurement has been receiving increasing attention, length, voltage, and other parameters can be
23、 transformed into a frequency measurement and related technologies to determine. Based on the more traditional method of synchronization cycle, and has proposed a multi-cycle synchronization and quantitative method of measuring delay frequency method. The most simple method of measuring the frequenc
24、y of direct frequency measurement method. Direct Frequency Measurement is scheduled to enter the gate signal pulse, the adoption of the necessary counting circuit, the number of pulses are filled to calculate the frequency or analyte signal cycle. In the direct frequency measurement on the basis of
25、the development of multi-cycle synchronous measurement method, in the current frequency monitoring system to be more widely used. Multi-cycle synchronization frequency measurement technology actual gate time is not fixed value, but the measured signals in the whole cycle times, and the measured sign
26、al synchronization, thereby removing the measured signal count on when the word 1 error, measurement accuracy greatly improved, and reached in the entire spectrum of measurement, such as precision measurement.In the time-frequency measurement method, the multi-cycle synchronization is a high precisi
27、on, but still unresolved a word error, mainly because of the actual gate edge and standard frequency synchronization is not filling pulse edge Tx=N0T0-t2+t1, if accurately measured short interval t1 and t2, will be able to accurately measure time intervals Tx, eliminating a word counting error, so a
28、s to further enhance accuracy. To measure a short time interval t1 and t2, commonly used analog interpolation method with the cursor or more combined cycle synchronization, although accuracy is greatly improved, but eventually failed to resolve a word error this fundamental issue, but these methods
29、equipment complex and not conducive to the promotion. To obtain high precision, fast response time, simple structure and the frequency and time measurement method is relatively difficult. Judging from the structure as simple as possible at the same time take into account the point of view of accurac
30、y, multi-cycle synchronization and delay based on the quantitative methods in a short period of time interval measurement, achieved within the scope of broadband, such as high-resolution measurement accuracy. Quantified by measuring short time intervals Delay Photoelectric signal can be in a certain
31、 stability in the medium of rapid spread, and in different media have different delay. By signals generated by the delay to quantify, and gave a short period of time interval measurement. The basic principle is that delay serial, parallel count, and different from the traditional counter serial numb
32、er, that is, to signal through a series of delay unit, the delay unit on the delay stability, under the control of the computer Delay on the state of high-speed acquisition and data processing, for a short period of time to achieve accurate measurement interval.Delay quantitative thinking depend on
33、the realization of the delay stability delay unit, the unit depends on the resolution of the delay time delay element. Delay device as a unit can be passive conduit, or other active devices gate circuit. Among them, Traverse shorter delay time (nearly the speed of light transmission delay), the gate
34、 delay time longer. Taking into account delays can be predictive ability final choice of the CPLD devices, the realization of the short time interval measurement. Will be the beginning of a short time interval signal sent delay in the transmission chain, when the advent of the end of signal, this si
35、gnal delay in the delay in the chain latch state, read through the CPU, the judge signal a delay unit on the few short-term time interval can be the size of the unit decided to delay resolution of the unit delay time. Generally speaking, in order to measure both short interval, the use of two module
36、s delay and latches, but in reality, given the time software gate large enough to allow completion from the number of CPU operation, which can be measured in the time interval taken before the end of a short period of time at t1 corresponding delay the number of units through the control signals mus
37、t be used only a delay and latches units, it saves CPLD internal resources. Synchronization and multi-cycle latency to quantify the method of combining The formula is: T=n0t0+n1t1-n2t1On, n0 for the filling pulse of value; t0 for filling pulse cycle, that is 100 ns; n1 for a short period of time at
38、t1 corresponding delay the number of modules; n2 for a short period of time at t2 corresponding delay unit Number; t1 quantify delay devices for the delay delay unit volume (4.3 ns). In this way, using multi-cycle synchronization and realized the gate and measured signal synchronization; Delay of us
39、ing quantitative measurement of the original measured not by the two short intervals, to accurately measure the size of the actual gate, it raised frequency measurement accuracy. The frequency synthesizer output frequency signal can only be transferred to the minimum 10 Hz, XDU-17 as a standard of m
40、easurement can be calculated prototype frequency measurement accuracy. For example, the measured signal is measured at 15. MHz MHz signal to 5., from the calculation can be seen above, the resolution of the prototype has reached ns order of magnitude below from the perspective of theoretical analysi
41、s to illustrate this point.It has been anal yzed,multi-cycle synchronization frequency measurement, the measurement uncertainty: When the input f0 10 MHz, 1 s gate time, the uncertainty of measurement of 110-7/s. When the measurement and quantification of delay circuit with short intervals combined,
42、 the uncertainty of measurement can be derived from the following. In the use of cycle synchronization, multi-analyte Tx for the cycle value of T0 time base for the introduction of the cycle. Tx= NT0+t1-t2 Delay circuit and quantitative combined: Tx= NT0+(N1-N2)tdTx Here, Tx not for the accuracy of
43、the measurement. On the decline of the share: Tx2tdFrom the details of the measuring accuracy of this method depends on the td, and its direct impact on the stability and size of the uncertainty of measurement. Therefore, the application of methods, counters can be achieved within the entire frequen
44、cy range, such as the accuracy of measurement, and measurement accuracy is significantly improved, measuring improvement in resolution to 4.3 ns, and the elimination of the word a theoretical error, the accuracy is increased by 20 times. CONCLUSION This paper presents a new method of measuring frequ
45、ency. Based on the frequency of this method of digital integrated circuit in a CPLD, greatly reduced the volume of the entire apparatus, improved reliability, and a high-resolution measurements.5 、Frequency of VHDL DesignALTERA use of the FPGA chip EPF10K10 companies, the use of VHDL programming lan
46、guage design accuracy of frequency, given the core course. ISPEXPER simulation, design verification is successful, to achieve the desired results. Compared to the traditional frequency of FPGA simplify the circuit board design. Increased system design and the realization of reliability, frequency me
47、asurement range of up to 100 MHz and achieve a digital system hardware and software, which is digital logic design the new trend.The design uses the AL TERA EPF10K FPGA chip, the chip pin the delay of 5 ns, frequency of 200 MHz， the standardization of application VHDL hardware description language h
48、as a very rich data types, the structure of the model of a complex digital system logic design and computer simulation, and gradually improve after the automatic generation integrated to meet the requirements of the circuit structure of the digital logic can be realized, then can be downloaded to pr
49、ogrammable logic devices, to complete design tasks.数字频率计的介绍数字频率计是通信设备、音、视频等科研生产领域不可缺少的测量仪器。采用Verilog HDL编程设计实现的数字频率计，除被测信号的整形部分、键输入部分和数码显示部分外，其余全部在一片FPGA芯片上实现。整个系统非常精简，且具有灵活的现场可更改性。1、 等精度测频原理频率的测量方法主要分为2种方法：（1） 直接测量法，即在一定的闸门时间内测量被测信号的脉冲个数。（2） 间接测量法，例如周期测频法、VF转换法等。间接测频法仅适用测量低频信号。基于传统测频原理的频率计的测量精度将随被测信号频率的下降而下降，在实际中有较大的局限性，而等精度频率计不但具有较高的测量精度，而且在整个频率区