屏参数设置说明(共5页).doc

上传人:飞****2 文档编号:13373057 上传时间:2022-04-29 格式:DOC 页数:5 大小:37KB
返回 下载 相关 举报
屏参数设置说明(共5页).doc_第1页
第1页 / 共5页
屏参数设置说明(共5页).doc_第2页
第2页 / 共5页
点击查看更多>>
资源描述

《屏参数设置说明(共5页).doc》由会员分享,可在线阅读,更多相关《屏参数设置说明(共5页).doc(5页珍藏版)》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。

1、精选优质文档-倾情为你奉上/ A panel struct type used to specify the panel attributes, and settings from Board layout1: const char *m_pPanelName; PanelName 屏的名称2: MS_U8 m_bPanelDither :1; Sub BK VOP_36, bPanelDither =10X2D05, bPanelDither =00X2D003: APIPNL_LINK_TYPE m_ePanelLinkType :4; Sub BK VOP_44 , LVDS =0x11

2、, RSDS =0x004: m_bPanelDualPort :1; Sub VOP_430, MOD_941, 5: MS_U8 m_bPanelSwapPort :1; Sub MOD_940 6: MS_U8 m_bPanelSwapOdd_ML :1; Sub MOD_9212 7: MS_U8 m_bPanelSwapEven_ML :1; Sub MOD_9214 8 : MS_U8 m_bPanelSwapOdd_RB :1; Sub MOD_9211 9: MS_U8 m_bPanelSwapEven_RB :1; Sub MOD_9213 11: MS_U8 m_bPane

3、lSwapLVDS_POL :1; Sub MOD_80512: MS_U8 m_bPanelSwapLVDS_CH :1; Sub MOD_806 13: MS_U8 m_bPanelPDP10BIT :1; Sub MOD_80314: MS_U8 m_bPanelLVDS_TI_MODE :1; Sub MOD_802, 说明当前的panel是不是TI mode15: MS_U8 m_ucPanelDCLKDelay; Sub MOD_948:11, 16: MS_U8 m_bPanelInvDCLK :1; Sub MOD_944, 17: MS_U8 m_bPanelInvDE :1

4、; Sub MOD_942, 18: MS_U8 m_bPanelInvHSync :1; Sub MOD_941219: MS_U8 m_bPanelInvVSync :1; Sub MOD_943, 20: MS_U8 m_ucPanelDCKLCurrent; Sub VOP_8E6:7, 21: MS_U8 m_ucPanelDECurrent; Sub VOP_8E4:5,22: MS_U8 m_ucPanelODDDataCurrent; Sub VOP_8E2:323:MS_U8 m_ucPanelEvenDataCurrent; Sub VOP_8E0:124: MS_U16

5、m_wPanelOnTiming1; time between panel & data while turn on power25: MS_U16 m_wPanelOnTiming2; time between data & back light while turn on power26: MS_U16 m_wPanelOffTiming1; time between back light & data while turn off power27: MS_U16 m_wPanelOffTiming2; time between data & panel while turn off po

6、wer28: MS_U8 m_ucPanelHSyncWidth; Sub VOP_027:029: MS_U8 m_ucPanelHSyncBackPorch; no register setting, provide value for query only, not support Manuel VSync Start/End nowVOP_0410:0 VSync start = Vtt - VBackPorch VsyncWidth, VOP_0610:0 VSync end = Vtt VbackPorch30: MS_U8 m_ucPanelVSyncWidth; MS_U8 m

7、_ucPanelVBackPorch; 31: MS_U16 m_wPanelHStart; Sub VOP_0811:0, DE H Start (PANEL_HSYNC_WIDTH + PANEL_HSYNC_BACK_PORCH)32: MS_U16 m_wPanelVStart; Sub VOP_0C11:033: MS_U16 m_wPanelWidth; DE width (VOP_0A11:0 = HEnd = HStart + Width - 1)34 :MS_U16 m_wPanelHeight; DE height (VOP_0E11:0= Vend = VStart +

8、Height - 1)35: MS_U16 m_wPanelMaxHTotal; Reserved for future using.36: MS_U16 m_wPanelHTotal; Sub VOP_1811:037: MS_U16 m_wPanelMinHTotal; Reserved for future using.38: MS_U16 m_wPanelMaxVTotal; Reserved for future using.39: MS_U16 m_wPanelVTotal; Sub VOP_1A11:040: MS_U16 m_wPanelMinVTotal; Reserved

9、for future using.41: MS_U8 m_dwPanelMaxDCLK; Reserved for future using.42: MS_U8 m_dwPanelDCLK; Sub LPLL_0F23:0 ,0x3100_107:0, 0x3100_0F15:043: MS_U8 m_dwPanelMinDCLK; Reserved for future using.44: MS_U16 m_wSpreadSpectrumStep; MS_U16 m_wSpreadSpectrumSpan; move to board define, no use now.45: MS_U8

10、 m_ucDimmingCtl; MS_U8 m_ucMaxPWMVal; MS_U8 m_ucMinPWMVal; Initial Dimming Value/ Max Dimming Value/ Min Dimming Value46: MS_U8 m_bPanelDeinterMode :1; no use now47: E_PNL_ASPECT_RATIO m_ucPanelAspectRatio; Panel Aspect Ratio, provide information to upper layer application for aspect ratio setting.4

11、8: MS_U16 m_u16LVDSTxSwapValue; Sub MOD_E60:15, 49: APIPNL_TIBITMODE m_ucTiBitMode; Sub MOD_961:0, 当颜色不对的时候,就可以调整这个设定来试验。50: APIPNL_OUTPUTFORMAT_BITMODE m_ucOutputFormatBitMode;Sub MOD_926:7, 10: 8bit, 01: 6bit :other 10bitDefine panel output format bit mode. The default value is 10bit, becasue 8bit

12、 panel can use 10bit config and 8bit config. But 10bit panel(like PDP panel) can only use 10bit config. And some PDA panel is 6bit51: MS_U8 m_bPanelSwapOdd_RG :1;MS_U8 m_bPanelSwapEven_RG :1;MS_U8 m_bPanelSwapOdd_GB :1; MS_U8 m_bPanelSwapEven_GB :1; Sub MOD_922:5, Odd_RG: bit3, Odd_GB: bit2 , Even_R

13、G bit5, Even_GB bit452: MS_U8 m_bPanelDoubleClk :1; LPLL_067 ,LVDS dual mode56: MS_U32 m_dwPanelMaxSET; MS_U32 m_dwPanelMinSET; 这个值会限定FPLL LOCK 的范围,也就是LPLL_D5D6D757: APIPNL_OUT_TIMING_MODE m_ucOutTimingMode; Define which panel output timing change mode is used to change VFreq for same panel, 目前有三种选择E_PNL_CHG_DCLK,E_PNL_CHG_HTOTAL,E_PNL_CHG_VTOTAL, 后面两者都是为了保持DCLK 不变而修改HTOTAL/VTOTAL.58: MS_U8 m_bPanelNoiseDith :1; Sub PAFRC_7E3Note 以上寄存器都是8bit Address专心-专注-专业

展开阅读全文
相关资源
相关搜索

当前位置:首页 > 教育专区 > 教案示例

本站为文档C TO C交易模式,本站只提供存储空间、用户上传的文档直接被用户下载,本站只是中间服务平台,本站所有文档下载所得的收益归上传人(含作者)所有。本站仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。若文档所含内容侵犯了您的版权或隐私,请立即通知淘文阁网,我们立即给予删除!客服QQ:136780468 微信:18945177775 电话:18904686070

工信部备案号:黑ICP备15003705号© 2020-2023 www.taowenge.com 淘文阁