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1、外文文献：Embedded Systems Design using the TI MSP430 Series up to larger 60k ROM, 2k RAM, with prices in the $10range devices. Currently, there are at least 40 flavors available, with more being added regularly. The devices are split into three families: the MSP430x3xx, which is a basic unit, the MSP430
2、x1xx, which is a morefeature-rich family, and the MSP430x4xx, which is similar to the 1xx, witha built in LCD driver. You willfind these referred to as 1xx, 3xx, and 4xxdevices throughout this book.Part Numbering ConventionPart numbers for MSP430 devices are determined based on their capabilities. A
3、ll device part numbers follow the following template:MSP430M tFa F bM c25 / 20M: Memory Type C: ROMF: Flash P: OTPE: EPROM for developmental use. There are few of these.F a, F b: Family and Features 10, 11: Basic12, 13: Hardware UART14:Hardware UART, Hardware Multiplier 31, 32: LCD Controller33:LCD
4、Controller, Hardware UART, Hardware Multiplier41:LCD Controller43:LCD Controller, Hardware UART44:LCD Controller, Hardware UART, Hardware Multiplier Mc:Memory Capacity0: 1kb ROM, 128b RAM1: 2kb ROM, 128b RAM2: 4kb ROM, 256b RAM3: 8kb ROM, 256b RAM4: 12kb ROM, 512b RAM5: 16kb ROM, 512b RAM6: 24kb ROM
5、, 1kb RAM7: 32kb ROM, 1kb RAM8: 48kb ROM, 2kb RAM9: 60kb ROM, 2kb RAMExample: The MSP430F435 is a Flash memory device with an LCDcontroller, a hardware UART, 16 kb of code memory, and 512 bytes of RAM.The part numbering scheme described above is a bit fragmented. Thereare common features not consist
6、ently represented type of ADC, number oftimers, etc, and there are some otherinconsistencies for example, the 33family has the multiplier, but the 13 and 43s do not. I would recommendagainst selecting parts based on their numbering scheme. Rather, once youhave a vague idea of your requirements, go t
7、o the TI website www.TI.com,and use their parametric sort feature.Architecture: CPU and MemoryAs discussed in chapter 1, the MSP430 utilizes a 16-bit RISC architecture, which is capable of processing instructions on either bytes or words. TheCPU is identical for all members of the 430 family. It con
8、sists of a 3-stageinstruction pipeline, instruction decoding, a 16-bit ALU, four dedicated-useregisters, and twelve working or scratchpad registers. The CPU is connected to its memory through two 16-bit busses, one for addressing, and theother for data. Allmemory, including RAM, ROM, information mem
9、ory, special function registers, and peripheral registersare mapped into a single, contiguous address space.This architecture is unique for several reasons. First, the designers at Texas Instruments have left an awful lot of space for future development. Almost half the Status Register remains avail
10、able for future growth, roughly half of the peripheral register space is unused, and only six of the sixteen available special function registers are implemented.Second, there are plenty of working registers. After years of having one or two workingregisters, I greatly enjoyed my first experience wi
11、th the twelve 16-bit CPU scratchpads. Theprogramming style is slightly different, and can be much more efficient, especially in the hands of a programmer who knows how to use this feature to its fullest.Third, this architecture is deceptively straightforward. It is very flexible, and the addressing
12、modes are more complicated than most other smallprocessors. But, beyond that, this architecture is simple, efficient and clean. There are twobusses, a single linear memory space, a rather vanilla processor core, and all peripherals are memory-mapped.CPU FeaturesThe ALUThe 430 processor includes a pr
13、etty typical ALUarithmetic logic unit. The ALU handlesaddition, subtraction, comparison and logicalAND,OR, XORoperations. ALU operationscan affect the overflow, zero, negative, and carry flags. The hardware multiplier, which is notavailable in all devices, is implemented as a peripheral device, and
14、is not part of the ALU seeChapter 6.Working RegistersThe 430 gives the developer twelve 16-bit working registers, R4 through R15. R0 through R3 are used for other functions, as described later. They are used for register mode operations see Addressing Modes, Chapter 8, which are much more efficient
15、than operations which require memory access. Some guidelines for their use:Use these registers as much as possible. Any variable which is accessed often shouldresidein one of these locations, for the sake of efficiency.Generally speaking, you may select any of these registers for any purpose, either
16、 dataor address. However, some development tools will reserve R4 and R5 for debuginformation. Different compilers will use these registers in different fashions, as well.Understand your tools.Be consistent about use of the working registers. Clearly document theiruse. I havecode,writtenabout 8months
17、ago, thatperformsextensive operations onR8,R9,andR15. Unfortunately, I dont know today what the values in R8, R9 and R15 represent.This was code I wrote to quickly validate an algorithm, rather than production code, so Ididnt document it sufficiently. Now, it is relative gibberish. Dont let this hap
18、pen to you.No matter how obvious or trivial register use seems, document it anyway.Constant GeneratorsR2 and R3 function as constant generators, so that register mode may be used instead ofimmediate mode for some common constants. R2 is a dualuse register. It serves as the Status Register, as well.
19、Generated constants include some common single-bit values 0001h, 0002h, 0004h, and 0008h, zero 0000h, and an all 1s field 0FFFFh. Generation is based on the WS value in the instruction word, and is described by the table below.WSvalue in R2value in R3 000000h010 absolute mode0001h100004h0002h110008h
20、0FFFFhProgram CounterThe Program Counter is located in R0. Since individual memory location addresses are 8-bit, but all instructions are 16 bit, the PC is constrained to even numbers i.e. the LSB of the PC is always zero. Generally speaking, itis best to avoid direct manipulation of the PC. One exc
21、eption to this rule of thumb is the implementation of a switch, where the codejumps to a spot, dependent on a given value. I.e., if value=0, jump to location0, if value=1,jump to location1, etc. This process is shown in Example 3.1.Example 3.1 Switch Statement via Manual PC ControlMovvalue,R15；put t
22、he switch value into R15CmpR15,#8；range checkingJgeoutofrange；if R157,do not use PC switchCmp#0,R15；more range checkingJnoutofrange；RlaR15；multiply R15 by two,since PC is always evenRlaR15；double R15again,sincesymbolic jmp is 2 words longAdd R15,PC ；PC goes to proper jump Jmp value0Jmp value1 Jmp va
23、lue2 Jmp value3 Jmp value4 Jmp value5 Jmp value6 Jmp value7OutofrangeJmp RangeErrorThis is a relativelycommon approach, and most C compilers willimplement switch statements withsomething similar.When implementingthismanually i.e.,inassemblylanguage, the programmer needs to keep several things in min
24、d:Always do proper range checking. In the example, we checked for conditionsoutside both ends of the valid range. If this is not performed correctly, the code canjump to an unintended location.Pay close attention to the addressing modes of the jump statements. The second doubling ofR15, prior to the
25、 add statement, is added because the jump statement requires two words when symbolic mode addressing is used.Be careful that none of your interrupt handlers have the potential to affect your value register R15 in the example. If the interrupt handler needs to use one of these registers, the handler
26、needs to store the value to RAM first. The most common procedure is to push the register to the stack at the beginning of the ISR, and to pop the register at the end of the ISR. See Example 3.2.Example 3.2 Push/Pop Combination in ISR Timer_A_Hi_InterruptPushR12；We will use R12MovP1IN,R12 ；use R12 as
27、 we please RlaR12RlaR12MovR12&BAR；Done with R12PopR12；Restore previous value to R12 Reti；return from interruptORG0FFF0hDWTimer_A_Hi_Interrupt Status RegisterThe Status Register is implemented in R2, and is comprised of various system flags. Theflags are all directly accessible by code, and all but t
28、hree of them are changed automatically by the processor itself. The 7 most significant bits are undefined. The bits of the SR are:.The Carry Flag C Location: SR0 the LSBFunction: Identifies when an operation results in a carry. Can be set or cleared by software,or automatically.1=Carry occurred 0=No
29、 carry occurred.The Zero Flag ZLocation: SR1Function: Identifies when an operation results in a zero. Can be set or cleared by software, or automatically.1=Zero result occurred 0=Nonzero result occurred.The Negative Flag N Location: SR2Function: Identifies when an operation results in a negative. Ca
30、n be set or cleared by software, or automatically. This flag reflects the value of the MSB of the operation result Bit 7 for byte operations, and bit15 for word operations.1=Negative result occurred 0=Positive result occurred.The Global Interrupt Enable GIE Location: SR3Function: Enables or disables
31、 all maskable interrupts. Can be set or cleared by software, or automatically. Interrupts automatically reset this bit, and the reti instruction automatically sets it.1=Interrupts Enabled 0=Interrupts Disabled.The CPU off bit CPUOff Location: SR4Function: Enables or disables the CPU core. Can be cle
32、ared by software, and is reset by enabled interrupts. None of the memory, peripherals, or clocks are affected by this bit. This bit is used as a power saving feature.1=CPU is on 0=CPU is off.The Oscillator off bit OSCOff Location: SR5Function: Enables or disables the crystal oscillator circuit LFXT1
33、. Can be cleared by software, and is reset by enabled external interrupts. OSCOff shuts down everything, including peripherals. RAM and register contents are preserved. This bit is used as a power saving feature.1=LFXT1 is on0=LFXT1 is off.The System Clock Generator SCG1,SCG0 Location: SR7,SR6Functi
34、on: These bits, along with OSCOff and CPUOff define the power mode of the device.The Overflow Flag V Location: SR8Function: Identifies when an operation results in an overflow. Can be set or cleared by software, or automatically. Overflow occurs when two positive numbers are added together, and the
35、result is negative, or when two negative numbers are added together, and the result is positive.1=Overflow result occurred0=No overflow result occurredFour of these flags Overflow,Negative, Carry, and Zero drive program control, via instructions such as cmp compare and jz jump if Zero flag is set. Y
36、ou will see these flags referred to often in this book, as their function represents a fundamental building block. The instruction set is detailed in Chapter 9, and each base instruction description there details the interaction between flags and instructions. As a programmer, you need to understand
37、 this interaction.Stack PointerThe Stack Pointer is implemented in R1. Like the Program Counter, the LSB is fixed as a zero value, so the value is always even. The stack is implemented in RAM, and it iscommon practice to start the SP at the top highest valid value of RAM. The push command moves theS
38、P down one word in RAM SP=SP-2, and puts the value to be pushed at the new SP. Pop doesthe reverse. Call statements and interrupts push the PC, and ret and reti statements pop the value from the TOS top of stack back into the PC. I have one simple rule of thumb for the SP: leaveit alone. Set the sta
39、ck pointer as part of your initialization, and dont fiddle with it manually after that. As long as you are wary of two stack conditions, the stack pointermanages itself. These two conditions are:Asymmetric push/pop combinations. Every push should have a pop. If you push a bunch of variables, and fai
40、l to pop them back out, it will come back to haunt you. If you pop an empty stack, the SP moves out of RAM, and the program will fail.Stack encroachment. Remember, the stack is implemented in RAM. If your program has multiple interrupts, subroutine calls, or manual pushes, the stack willtake up more
41、 RAM, potentially overwriting values your code needs elsewhere.Memory StructureSpecial Function RegistersSpecial function registers are, as you might have guessed,memory-mapped registers with special dedicated functions. There are, nominally, sixteen of these registers, at memory locations 0000h thr
42、ough 000Fh. However, only the first six are used. Locations 0000h and 0001h contain interrupt enables, and locations 0002h and 0003h contain interrupt flags. These are described in Chapter 3.Locations 0004h and 0005h contain module enable flags. Currently, only two bits are implemented in each byte.
43、 These bits are used for the USARTs.Peripheral RegistersAllon-chip peripheral registers are mapped into memory, immediately after the special function registers. There are two types of peripheral registers: byte-addressable, which are mapped in the space from 010h to 0FFh, and word-addressable, which are mapped from 0100h to 01FFh.RAMRAM always begins at location 0200h, and is contiguous up to its final add