《AB1562_Datasheet原版完整文件.docx》由会员分享，可在线阅读，更多相关《AB1562_Datasheet原版完整文件.docx（110页珍藏版）》请在taowenge.com淘文阁网|工程机械CAD图纸|机械工程制图|CAD装配图下载|SolidWorks_CaTia_CAD_UG_PROE_设计图分享下载上搜索。
1、 AB1562 DatasheetVersion:0.13Release date:20 March 2020 2020 Airoha Technology Corp.This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s). Airoha cannot grant you permission for any material that is owned by third parties. You may only us
2、e or reproduce this document if you have agreed to and been bound by the applicable license agreement with Airoha (“License Agreement”) and been granted explicit permission within the License Agreement (“Permitted User”). If you are not a Permitted User, please cease any access or use of this docume
3、nt immediately. Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited. THIS DOCUMENT IS PROVIDED ON AN “AS-IS” BASIS ONLY. AIROHA EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES OF ANY KIND AND SHALL IN NO EVENT BE LIABLE FOR ANY CLAIMS RELATING TO O
4、R ARISING OUT OF THIS DOCUMENT OR ANY USE OR INABILITY TO USE THEREOF. Specifications contained herein aresubject to change without notice.AB1562 DatasheetDocument Revision HistoryRevisionDateDescription0.1017 February 2020Initial release0.1113 March 2020Update Chapter 2.5 Audio systemUpdate Chapter
5、 6.2 Power0.1213 March 2020Update 1.4 Audio features overview0.1320 March 2020Add AB1561 to below chapters Chapter 1 System Overview Chapter 5 Pin Description Chapter 6 Electrical CharacteristicsUpdate Chapter1.5 Connectivity (Bluetooth) features overviewUpdate Chapter 3 Bluetooth RF Subsystem 2020
6、Airoha Technology CorpPage 4 of 110This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.FeaturesDSP Host processor Cadence HiFi
7、MiniAudio Engine DSP coprocessor with HiFi EP extension Maximum speed: 208MHz 32kB instruction cache and 8kB data cache with high hit rate and zero wait state 160kB instruction RAM with zero wait state 384kB data RAM with zero wait stateMemory System in Package (SiP) 16Mb low-power flash memory with
8、 0.1A deep-down current (typical condition) and maximum speed 104MHz Low latency 8kB system RAM (SYSRAM) with maximum speed 104MHzPlatform Dynamic Frequency Scaling (DFS) 17 DMA channels RTC timer Seven general purpose timers (GPTs) Watchdog timer (WDT) Capacitive Touch Control True random number ge
9、nerator Ambient temperature from -40C to 85CPeripheral Two I2C interfaces up to 3.4Mhz Two UART interfaces up to 3Mbps SPI master interfaces up to 52MHz PWM channels 12-bit AUXADC channelsBluetooth Fully compliant with Bluetooth core specification 5.2 Low-IF arc1hitecture with high degree of lineari
10、ty and high order channel filter Integrated T/R switch and balun Fully integrated PA provides 8dBm output power -94dBm sensitivity with interference rejection performance Baseband support dual mode (Bluetooth and Bluetooth LE) and isochronous channel Up to four simultaneous active ACL links Up to fo
11、ur simultaneous active Bluetooth LE links Support single SCO or eSCO link with CVSD/mSBC coding Support BLE1M/2MAudio Three uplink paths with analog/digital microphone input mode. The maximum sample rate is 192 KHz and data precision is 24-bit. One downlink path with maximum 192 KHz sample rate and
12、24-bit data precision. Class D amplifier Side-tone filter Two channel asynchronous sample rate convertero Anti-alias filtero 16/32-bit input/output data formatso frequency auto-tracking Hardware Active Noise Cancellation(ANC)o Feedforward ANCo Hybrid ANC (only AB1562A support) I2S master or slave mo
13、deso 16/24-bit data addressing formato mono or stereo data transactionso maximum sample rate 192KHz hardware gain controlPower management Two Buck regulators Three LDO regulators Li-ion battery charger for internal chargingPackage SQFN of 4mm*6.5mm, 44-lead, 0.4mm pitch packageAB1562 DatasheetTable
14、of ContentsDocument Revision History2Features3Table of Contents5List of Figures and Tables8System Overview11Product series11System architecture12Platform features overview12Host processor DSP subsystem12Memory summary13Peripheral interfaces summary13Security13Others13Audio features overview13Audio c
15、odec feature overview14Audio other functions feature overview14Connectivity (Bluetooth) features overview15Bluetooth RF15Bluetooth baseband15Power management unit (PMU) features overview16Package16Functional Description17DSP Host Processor17Cadence HiFi MiniAudio Engine DSP coprocessor with HiFi EP
16、extension17Cache controller18Local Memory18Memory Management19Interrupt19Platform description1919Boot mode19Trapping and mode selection19Bus Architecture20Clock source and structure22Clock architecture22Digitally controlled crystal oscillator2332kHz low-speed internal RC (EOSC32)24Low-power oscillat
17、or (LPOSC)24Phase locked loop25Peripheral description26General purpose input/output (GPIO)26Direct memory access (DMA)26General purpose timer (GPT)27True random number generator (TRNG)28Real time clock (RTC)28Pulse width modulation (PWM)28Inter-integrated circuit controller (I2C)29Universal asynchro
18、nous receiver/transmitter (UART)29 2020 Airoha Technology CorpPage 93 of 110This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited
19、.Serial peripheral interface (SPI)30Serial flash controller (SFC)34Audio system34General descriptions34Audio codec35Asynchronous sample rate converter46Audio frontend memory interface50Audio inter connection50Audio hardware gain50Audio Up-sampler51Audio Down-sampler51Audio PLL frequency tuner51I2S52
20、Active noise cancellation (ANC)57Audio system miscellaneous blocks58Connectivity System58Connectivity features overview58Connectivity system59Modem60Analog Baseband60Low-power oscillator (LPOSC)60Phase locked loop61Auxiliary ADC (AUXADC)62VAD (Voice amplitude detect)64Capacitive Touch Control65Block
21、 description65Functional specifications65Bluetooth RF Subsystem67Bluetooth description67Functional specifications67Basic data rate receiver specifications68Basic data rate transmitter specifications68Enhanced data rate receiver specifications69Enhanced data rate transmitter specifications70Bluetooth
22、 LE receiver specifications71Bluetooth LE transmitter specifications72Power Management Unit and Low-Power Control System73Low-power control system73General descriptions73PMU architecture for low-power operating mode73Power performance summary76Power Management / Regulation77Introduction77BUCK regula
23、tor78LDO regulator79Power management unit (PMU)79Li-ion battery charger80Pin Description82AB1562 and AB1562A82AB1562 and AB1562A ball diagram82AB1562 and AB1562A pin multiplexing86AB156187AB1561 ball diagram87AB1561 pin multiplexing91Electrical Characteristics96Absolute maximum ratings96AB1562 serie
24、s96Power96VDD33 LDO96VRF11 LDO97VDIG18 LDO97Battery charger97Electrostatic discharge (ESD) ratings98Operating conditions98AB1562 series98Peripheral interface105SPI master interface characteristics105Package Information107AB1562 series mechanical data of the package107List of Figures and TablesFigure
25、 1.2-1. AB1562 Series System Architecture12Figure 2.2-1. Block diagram20Figure 2.3-1. AB1562 series clock source architecture23Figure 2.3-2. Block diagram of APLL1 clock sources25Figure 2.4-1. Variety data paths of DMA transfers27Figure 2.4-2. DMA block diagram27Figure 2.4-3. PWM waveform29Figure 2.
26、4-4. Pin connection between SPI master and SPI slave30Figure 2.4-5. SPI transmission formats31Figure 2.4-6. Operation flow with and without PAUSE mode32Figure 2.4-7. CS de-assert mode32Figure 2.4-8. SPI master controller critical path sampling33Figure 2.4-9. SPI master controller SCK and data delay3
27、4Figure 2.5-1. AB1562 series Audio System Block Diagram34Figure 2.5-2. Block Diagram of Audio Uplink36Figure 2.5-3. Audio Uplink Block Diagram38Figure 2.5-4. Block Diagram of Audio Downlink41Figure 2.5-5. Audio Downlink Block Diagram43Figure 2.5-6. ASRC Block Diagram46Figure 2.5-7. 192 kHz to 96 kHz
28、 down-sample simulation result (FSO/FSI=0.500)48Figure 2.5-8. 44.1 kHz to 192 kHz up-sample simulation result (FSO/FSI=4.354)49Figure 2.5-9. I2S Timing Requirement Waveform54Figure 2.5-10. I2S Bus Protocol: I2S Format55Figure 2.5-11. I2S Bus Protocol: EIAJ Format55Figure 2.5-12. I2S Bus Protocol: LJ
29、 Format56Figure 2.5-13. I2S Bus Protocol: RJ Format56Figure 2.5-14. ANC Concept57Figure 2.5-15. Feed-forward ANC system57Figure 2.5-16. Hybrid ANC system58Figure 2.6-1. Link manager60Figure 2.7-1. Block diagram of APLL1 clock sources61Figure 2.7-2. Block diagram62Figure 2.7-3. Block diagram64Figure
30、2.8-1. Block diagram65Figure 3.1-1. Bluetooth RF transceiver system67Figure 4.1-1. AB1562 series PMU power grid73Figure 4.1-2. AB1562 series system power state74Figure 4.2-1. Power blocks78Figure 4.2-2. Buck regulators circuit79Figure 4.2-3. Voltage regulators circuit79Figure 4.2-4. Battery charger
31、circuit80Figure 4.2-5. Charging profile81Figure 5.1-1. AB1562 and AB1562A lead diagram and top view82Figure 5.1-2. AB1562 and AB1562A GPIO block diagram87Figure 5.2-1. AB1561 lead diagram and top view87Figure 5.2-2. AB1561 GPIO block diagram92Figure 6.6-1. SPI master interface timing diagram (CPHA=0
32、)105Figure 6.6-2. SPI master interface timing diagram (CPHA=1)106Figure 7.1-1. Outlines and dimensions of AB1562 series SQFN of 4mm*6.5mm, 44-lead, 0.4mm pitch package109Table 1.1-1. AB1562 product family11Table 1.3-1. AB1562 series peripherals13Table 2.1-1. Instruction RAM and Data Ram19Table 2.2-1
33、. Trapping pin list20Table 2.2-2. Trap pin electric characteristics20Table 2.2-3. AB1562 series bus connection21Table 2.3-1. DCXO Characteristics (TA = 25 oC, VDD = 1.1V unless otherwise stated) (1)23Table 2.3-2. Functional specifications of EOSC3224Table 2.3-3. LPOSC specifications24Table 2.3-4. AP
34、LL specifications25Table 2.4-1. SPI master interface30Table 2.5-1. Audio uplink Specifications36Table 2.5-2. MICBIAS specifications37Table 2.5-3. Audio Uplink Digital Filter Specifications in 8 KHz39Table 2.5-4. Audio Uplink Digital Filter Specifications in 16 KHz39Table 2.5-5. Audio Uplink Digital
35、Filter Specifications in 32 KHz39Table 2.5-6. Audio Uplink Digital Filter Specifications in 48 KHz39Table 2.5-7. Audio Uplink Digital Filter Specifications in 96 KHz39Table 2.5-8. Audio Uplink Digital Filter Specifications in 192 KHz39Table 2.5-9. Audio Downlink Specifications41Table 2.5-10. Audio D
36、ownlink Digital Filter Specifications in Voice Mode43Table 2.5-11. Audio Downlink Digital Filter Specifications in Audio Mode44Table 2.5-12. ASRC Digital Filter Specifications47Table 2.5-13. Comparison with Audio Codec, I2S Master and I2S Slave mode52Table 2.5-14. I2S Protocol Specifications52Table
37、2.5-15. I2S Bit Clock Jitter Percentage that generated from APLL53Table 2.5-16. I2S Word Select Clock Jitter Percentage that generated from APLL53Table 2.5-17. I2S Bit Clock Jitter Percentage that generated from XO53Table 2.5-18. I2S Word Select Clock Jitter Percentage that generated from XO53Table
38、2.5-19. I2S Timing Requirements54Table 2.7-1. LPOSC specifications60Table 2.7-2. APLL specifications61Table 2.7-3. Auxiliary ADC input channels62Table 2.7-4. Auxiliary ADC Specifications63Table 2.7-5. VAD input channels64Table 2.7-6. VAD Specifications64Table 2.8-1. Capacitive touch input channels65
39、Table 2.8-2. Touch Control Specifications66Table 3.2-1. Basic Data Rate receiver specifications68Table 3.2-2. Basic Data Rate transmitter specification68Table 3.2-3. Enhanced Data Rate Receiver Specifications69Table 3.2-4. Enhanced Data Rate transmitter specifications70Table 3.2-5. Bluetooth LE 1M r
40、eceiver specifications71Table 3.2-6. Bluetooth LE 2M receiver specifications71Table 3.2-7. Bluetooth LE 1M transmitter specification72Table 3.2-8. Bluetooth LE 2M transmitter specification72Table 4.1-1. Off, RTC, and sleep scenarios74Table 4.1-2. Active scenarios75Table 4.1-3. System Wakeup Source75
41、Table 4.1-4. Current consumption in different power modes76Table 5.1-1. AB1562 and AB1562A pin coordinates83Table 5.1-2. Acronym for pin types and I/O structure83Table 5.1-3. AB1562 series pin function description and power domain84Table 5.2-1. AB1561 pin coordinates88Table 5.2-2. Acronym for pin ty
42、pes and I/O structure88Table 5.2-3. AB1561 pin function description and power domain89Table 5.2-4. PinMux description93Table 5.2-5. RTC PinMux description93Table 5.2-6. Peripheral functions and signals94Table 6.1-1. Absolute maximum ratings for power supply96Table 6.1-2. Absolute maximum ratings for
43、 I/O power supply96Table 6.1-3. Absolute maximum ratings for voltage input96Table 6.1-4. Absolute maximum ratings for storage temperature96Table 6.2-1. VDD33 LDO97Table 6.2-2. VRF11 LDO97Table 6.2-3. VDIG18 LDO97Table 6.3-1. Battery Charger97Table 6.4-1. ESD electrical characteristic of AB1562 serie
44、s98Table 6.5-1. AB1562 series general operating conditions98Table 6.5-2. Recommended operating conditions for power supply98Table 6.5-3. Recommended operating conditions for voltage input99Table 6.5-4. Recommended operating conditions for operating temperature99Table 6.5-5. Electrical characteristic
45、s99Table 6.6-1. SPI master interface characteristics106System OverviewProduct seriesThe AB1562 product family provides different packages for different market purposes. Table 1.1-1 shows the comparison of the AB1562 series chipsets.Table 1.1-1. AB1562 product familyItemAB1562AB1562AAB1561ANCYesAudioMonoMonoStereoVBUS_UARTYesYesSystem BusSystem BusPIN MUXSystem architectureBRBT 5.XEDRBLEI-Cache32 KBD-Cache8 KBI-RAM160 KBD-RAM384 KBBlue ToothRFTensilica